Many thanks for your answer Igor,
So, if I understood well, there isn't the possibility to configure the MIPI receiver (iMX6 CSI in this case) to work with a transmitter that produce or not LP signals. But does it mean that the transmitter MUST produce LP signals for an appropriate exchange between iMX6 MIPI internal states?
If this is the case... I'm wrong with my design!!
In may case, the sensor has a parallel bus and the parallel to MIPI conversion is made by an FPGA. FPGA has 4 and not only 2 output for clock/data:
- 2 differential output for HS (High speed) transmission
- 2 single ended (1.2V) signals to connect by two external 50ohm resistor to clk/data p and clk/data n respectively.
For a MIPI bus with 4data lanes there are a total of 20 I/O:
- clk: clk HS p, clk HS n, clk LP p, clk LP n
- data0: data0 HS p, data0 HS n, data0 LP p, data0 LP n
- data1: data1 HS p, data1 HS n, data1 LP p, data1 LP n
- data2: data2 HS p, data2 HS n, data2 LP p, data2 LP n
- data3: data3 HS p, data3 HS n, data3 LP p, data3 LP n
When I made the design, I want to be honest, really I didn't understand nothing about what LP signals do. So I preferred to make an easier connetion where the two single ended output are not used and the two 50ohm resistor are connected both to ground. In this case, when the internal FPGA logic put the differential output in three-state, both lines (p and n) are tied together to low. With this configuration there isn't the possibility to put line to hi level (LP11 state) and after lo low level (LP01 and LP00) before an HS transmission.
I don't know what kind of MIPI receiver can work properly in this way but what I'm understanding now is that iMX6 MIPI interface CAN'T run without properly management of LP signals from TX side.
Before going to change my board :smileysad:... could you confirm, please, that there aren't any low level registers that I can change to "say" to iMX6 MIPI interface that during LP state both differential lines for clk/data will be always to 00 state?
Many many thanks.
