You can use the DCD settings we use in U-boot and convert it to a OpenOCD init script:
Regards,
Fabio Estevam
UPDATE: I was able to do lots of debugging using the DCD settings from u-boot as suggested. However, I have recently created an image that the iMX6SL ROM loads from SPI NOR FLASH at boot time (Internal Boot Mode) and this has broken my OpenOCD setup. It seems that if the CPU boots from internal boot mode (as opposed to Serial Downloader) then OpenOCD will not reset-init. It seems to be failing at the SDRAM configuration code but it is hard to say for sure.
Note that the code that I am loading from internal boot has been:
- a working u-boot.imx image
- a "dummy" executable that just loops at the reset vector
- a u-boot image that executes up to _main() and then busy waits
All of the above cases prevent OpenOCD from attaching. Any ideas about JTAG/OpenOCD configuration when the iMX6SL is in "Internal Boot" mode?
Got it. The SDRAM Chips must be reset at initialization because the internal boot ROM may have already initialized the RAM. The DCD code from U-BOOT does not do this.
Added to reset-init :
... Clocks, etc.
### DISABLE SDRAM CS 0/1, Resets the DDR Chips
## This is necessary for RAM that may have already been enabled with a DCD load
## before the HALT command stopped execution
mww phys 0x021b0000 0x03110000
... Start Memory Configuration ....
Thanks, but the problem is getting all of the "poke" mmw commands to initialize the SDRAM, Clocks, FLASH banks, drive strengths, etc for the particular board MCIMX6SL-EVK. I can dig through the schematic and data sheet but I had hoped that Freescale or a user had already done this and could provide the configuration.
As for the multiple cores, this is a Solo Lite board.
You can use the DCD settings we use in U-boot and convert it to a OpenOCD init script:
Regards,
Fabio Estevam