The problem was solved!!!!
The bit SCR_VAL_CLEAR to register SPDIF_SCR and is mask must be set to work..
The "validity" flag (bit 28 in each subframe, counting from preamble bit 0) was going out as 1 rather than 0, and per SP-DIF standard '1' denotes an *invalid* sample, like from a scratched CD giving read errors (though it's reversed again in i.MX6 SPDIF_SCR register, where the power-on default '0' in bit 5 means "send out 1s").
/kernel_imx/sound/soc/fsl/fsl_spdif.c
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
scr = SCR_TXFIFO_AUTOSYNC | SCR_TXFIFO_CTRL_NORMAL |
SCR_TXSEL_NORMAL | SCR_USRC_SEL_CHIP |
- SCR_TXFIFO_FSEL_IF8;
+ SCR_TXFIFO_FSEL_IF8 | SCR_VAL_CLEAR;
mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
- SCR_TXFIFO_FSEL_MASK;
+ SCR_TXFIFO_FSEL_MASK | SCR_VAL_MASK;
for (i = 0; i < SPDIF_TXRATE_MAX; i++)
clk_prepare_enable(spdif_priv->txclk[i]);
}