Alternate DDR1 for IMX23 - What defines or DDR settings need changing?

[ssdac]

A new ALLIANCE DDR1 (AS4C32M16D1-5TCN) is available now from Digikey (and elsewhere) for just $2.12 and there are 10,000 in stock in the US now.

We would like to use this in our IMX23 product due to great availability and very low cost.

Unfortunately , when I solder in the "compatible" Alliance DDR1 I get these messages (Linux and WinCe)

Undefined Instruction  r14_

Both data sheets are here

This is the Alliance  http://www.alliancememory.com/datasheets/pdf/ddr1/512M-AS4C32M16D1.pdf

This is the MICRON that is used witht the Freescale EVK and their BSP

http://www.micron.com/~/media/Documents/Products/Data%20Sheet/DRAM/DDR1/512Mb_DDR.pdf

We looked at the BSP for CE and see DDR setup in XLDR.C  (InitSDRAM) , but we have had no success modifing the code based on the 2 data sheets. So far we have lowered the clock to 96MHZ and changed drive levels (to both 4ma and 16ma) ..but we do not see any changes indicating this is helping to solve the problem.

If it is hardware or chip compatibility we see NO difference is the data sheets.

If it is timing, we do not see any other tools or settings beyond the DDR registers and Drive levels (see xldr-rev.c attached)

Here are the errors in both Linux and WinCE. If you have any suggestions for changing the WinCE,BSP we can try it right away as this is our primary OS.

Thanks!

John

LINUX  u-Boot

HTLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLFC
PowerPrep start initialize power...
Battery Voltage = 0.65V
No battery or bad battery                                       detected!!!.Disabling battery                                   voltage measurements./r/nLLCMay 11 201215:26:EMI_CTRL 0x1C08404

init_ddr_mt46v32m10Frac 0x92926192
LLLLLLLFCLJe cpu fr
Undefined Instruction
r14_

WINCE  (FreeScale EVK)

HTLC
BATT:1.52V
Ab5
+                  << this is our debug before calling InitSDram
LLJ              << The "L" character debug is in the ROM
Data Abort   << this is due to ALLIANCE DDR installation this sometimes says "prefetch abort"
r14_

Original Attachment has been moved to: xldr-rev1.c.zip

[rsa]

Hello Scott,

I stumbled upon the same Alliance DRAM as a replacement for our current memory and found it not working.

Did you ever get the Alliance AS4C32M16D1-5TCN to work with i.MX233 ?

[rsa]

I may have found the answer myself, hopefully someone at Freescale can comment on this because the datasheet is not very clear on it.

The alliance datasheet claims EMRS register needs to be written during init since it has an undefined value at power up.

The IMX23RM datasheet states on P631 (12-17) that enabling HW_DRAM_CTL05_EN_LOWPOWER_MODE enables the memory controller to use the initialization sequence and EMRS addressing.....

After having this bit set I was able to boot the IMX233 with AS4C32M16D1-5CTN whithout undefined instruction R14_  error (in fact memory testing is okay now).

My guess is that standard init procedure does not address the EMRS but only MRS.

[ssdac]

It seems there is a tool from Freescale they used to create the defines for different SDRAM  and DDR .

In xldr.c (WinCE) the DDR1and mDDR defines (DRAM 0:40 registers) seem to have bee "created" from a utility or macro.

Does anyone know about this configuration tool? 

All we've found so far it this for MX50 and MX28 (mDDR specific) ... but nothing for the MX23

Board Bring-up and DDR Initialization Tools

Thanks

SR

[Yuri]

  Appears, we do not have relatively simple tool or Excel table for i.MX23.

Basically Denali tools are used by Freescale to generate custom register

settings for the  i.mx233 and other STMP derivatives that use Denali IP in the

EMI block.

< https://www.denali.com/en/support/index.jsp >