Accessing mode register MR33 in LPDDR4 with i.MX8

[twmemphis]

Hello!

there are LPDDR4 DRAMs which have integrated ECC error correction functionality (IME4G32L4HABG). These devices even have additional ERROR-pins which could be used to trigger an interrupt routine or reset the application upon detected errors.

The datasheet of these LPDDR4 describes that a certain bit in mode register MR33 needs to be set to activate these error-pins. To read out if the error was a single or a double bit error, there are also certain bits in MR33 that need to be read.

Is it possible to access MR33 with the i.MX8 ?

In MRCTRL0  bit 15-12 an address of the mode-register can be set, but it looks as if only MR0 to MR7 are supported. Even if all 4 bits were used for the address, this would only allow addressing max MR15.

But maybe there is some other trick to init MR33 during boot and eventually also to read MR33 during runtime of the application? Would you know that?

Regards,

Thorsten

[igorpadykov · Accepted solution]

Hi Thorsten

MRCTRL1 can be used for write, as stated in sect.9.3.3.1.7 Mode Register Read/Write

Control Register 1 (MRCTRL1) i.MX8MQ Reference Manual

i.MX 8M Dual/8M QuadLite/8M Quad Applications Processors Reference Manual

"For LPDDR2/LPDDR3/LPDDR4, MRCTRL1[15:0] are interpreted as [15:8]
MR Address [7:0] MR data for writes, don't care for reads."

I am afraid no option for read.

Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[twmemphis]

Ah, now I got it. the MRCTRL0  bits 15-12 I was looking at are NOT for LPDDR4. For some reason I understood it the opposite way. Ok, now it is clear. MRCTRL1 will do!