Accessing Low power real time SPI's From A55 core in imx93

[logan3c3]

Is it possible to access the SPI that are dedicated to Low power real-time domain. Can TRDC be used to configure the same. if so can anybody share steps for that?

#IMX93

[danielchen]

A practical experiment to dump the LPSPI version ID in U-Boot demonstrates that the Arm Trusted Firmware (ATF) does not configure the TRDC to block access to LPSPI1-2 by the Cortex-A55:

u-boot=> md.l 0x44360000 1
44360000: 02000004                             ....
u-boot=> md.l 0x44370000 1
44370000: 02000004                             ....
u-boot=> md.l 0x42550000 1
42550000: 02000004                             ....

As demonstrated, the only configuration necessary to access LPSPI1-2 from Cortex-A55 is to read and write the appropriate addresses.

Regards

Daniel

[danielchen]

Hi @logan3c3 :

From I.MX93 Reference Manual , we know that two SPI devices in the Low Power real time real time domain.  -> Connectivity and I/O block.  These are LPSPI1 and LPSPI2 as show in Figure 2 in RM.

All 8 LPSPI hosts can be accessed from the Linux BSP running on the Cortex-A55 complex.  Please refer to the memory map in the RM , section 2.2

Regards

Daniel

[lapohab]

Daniel, your ignorance about IMX is so extreme that you can't even understand logan3c3's question. What nonsense are you spouting here every day? Do you want me to list all the links to your nonsense?