Access PCIe register in CM7 IMX8MP

[Majidbahmani]

Hi,

I am testing pcie through imx8mp. I would like to read VendorID and DeviceID through CM7 according to imx8mp.dtsi the pcie node is as follows:  

pcie: pcie@33800000 {
compatible = "fsl,imx8mp-pcie";
reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
reg-names = "dbi", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x00 0xff>;
ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */
<0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
num-lanes = <1>;
num-viewport = <4>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
fsl,max-link-speed = <3>;
linux,pci-domain = <0>;
power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>,
<&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>;
reset-names = "apps", "turnoff";
phys = <&pcie_phy>;
phy-names = "pcie-phy";
status = "disabled";
};

and when I read pcie in linux environment I found that vendorId and deviceId of pcies are stored in stored in address 0x33800000 and 0x1ff00000:

root@imx8mp-lpddr4-evk:~# lspci -n
00:00.0 0604: 16c3:abcd (rev 01)
01:00.0 0200: 1b4b:2b42 (rev 11)
root@imx8mp-lpddr4-evk:~# devmem2 0x1ff00000
/dev/mem opened.
Memory mapped at address 0xffffbd0c4000.
Read at address 0x1FF00000 (0xffffbd0c4000): 0x2B421B4B
root@imx8mp-lpddr4-evk:~# devmem2 0x33800000
/dev/mem opened.
Memory mapped at address 0xffffbaa5d000.
Read at address 0x33800000 (0xffffbaa5d000): 0xABCD16C3

But when I read the address in CM7 only the value 0x33800000 is correct and the value of  0x1ff00000 is 0x00;

Do you know what should I do to access pcie values in address 0x1ff00000?

Thanks.

[Alejandro_Salas]

Hello @Majidbahmani 

I hoe you are doing well.

It appears the 0x1ff00000 address is not accesible for Cortex M, you can see this on reference Manual.

2.2 Cortex-A53 Memory Map:

2.3 Cortex-M7 Memory Map:

As you can see in Cortex M is just defined the 0x33800000 register to access the PCIe Registers.

Best regards,

--... ...--

Salas.

[Majidbahmani]

Hi @Alejandro_Salas 

Great! You are right. I am testing with IMX8MP_EVK and the Wi-Fi module has connected to the processor through PCIe.

Does it mean that I can not access directly to this module (or any other device which might be connect to PCIe) in CM7?

Thank you for your helpful reply.

[Alejandro_Salas]

Hello @Majidbahmani 

As you can see the CM7 can access from 3380_0000 to 33BF_0000 that those are the PCI Registers, but maybe you can try to use RPMSG to send those IDs from Cortex A to Cortex M.

You can see the rpmsg_lite_str_echo_rtos example in our SDK for Cortex M.

I hope this can helps to you.

Best regards,

--... ...--

Salas.