About voltage control of DVFS for i.MX6Solo

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About voltage control of DVFS for i.MX6Solo

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yuuki
Contributor V

Dear all,

We have some questions about DVFS.
Would you teach about the following contents?

Q1)
The following contents are explained in section 10.4.1.4.1 Power distribution of the reference manual.

10.4.1.4.1 Power distribution (P.524)
"Cortex-A9 Core Platform - DVFS and power gating."

Does this mean LDO_DIG(ARM) of "Figure 10-6. i.MX 6Solo/6DualLite Power Tree"(P.518)?

Q2)
I understand that DVFS controls the voltage by using PMU_MISC2n register.

Does DVFS control LDO_DIG(SoC) and LDO_DIG(PU)?
Or Does DVFS control only LDO_DIG(ARM)?

Best Regards,
Yuuki

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This an automatic process.

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi yuuki

1. correct, it is LDO_DIG(ARM) of "Figure 10-6"

2. DVFS control only LDO_DIG(ARM) with PMU_REG_CORE.

Best regards

igor

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yuuki
Contributor V

Dear Igor-san,

Thank you for your support.

I found the following description.

i.MX_6_Linux_Reference_Manual.pdf:

- Chapter 24 CPU Frequency Scaling (CPUFREQ) Driver

24.1 Introduction

"The CPU frequency scaling device driver allows the clock speed of the CPU to be
changed on the fly. Once the CPU frequency is changed, the voltage VDDCORE,
VDDSOC and VDDPU are changed to the voltage value defined in device tree scripts
(DTS)."

Therefore I understand that DVFS can control also LDO_DIG(SoC) and LDO_DIG(PU).


Best Regards,
Yuuki

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