About the timing of the 24MHz Xtal stability and Reset de-assertion at a cold start of i.MX28

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About the timing of the 24MHz Xtal stability and Reset de-assertion at a cold start of i.MX28

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Contributor V

Would you teach about the timing of 24MHz Xtal oscillation stability and Reset de-assertion at a cold start of i.MX28?

The timing which I would like to know is the following.
Power-on(VDD5V power) => 24MHz Xtal oscillation stabile => Reset de-assertion

It is the purpose to check whether Xtal is oscillating correctly.


I am referring to the following.

IMX28CEC.pdf (Rev3):
- 3.1.7 Reset Timing(P.18)
"Because the i.MX28 is a PMU and an SoC, power-on reset is generated internally and there is no timing
requirement on external pins.
The i.MX28 can be reset by asserting the external pin RESETN for at least 100 mS and later deasserting
RESETN."

This time, VDD5V power pin is used.
In this case, according to 11.3.3 Power-Up Sequence of Reference manuals,  I think that the time to Reset de-assertion is the following.

VDD5V power pin > 4.25 V for 100 ms

However, I was not able to find the description about the relation between 24MHz Xtal statement and Reset de-assertion.

Best Regards,

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NXP Employee
NXP Employee

Hi, Yuuki

sorry for the late response because of Chinese New Year vacation.

yes, your understanding for i.mx6 is right.

I don't think i.mx28 has the same timg requirement as i.mx6.

while, 24M crystal is stable before ROM code running should be a MUST for i.mx28 since you don;t use 32.768k.

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Contributor V

Hi, Weisong Liu-san,

Thank you for your reply.

I referred to the errata of i.MX6.

"Adds 1.5 ms to the startup sequence."
=>
I surmise that iMX6 waits to start internal ROM until 24MHz Xtal is stablized.

Is my understanding right?

For i.MX28,

Is i.MX28 the same as that too?

Should the stable time of 24MHz Xtal be 1.5ms or less?


Best Regards,

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NXP Employee
NXP Employee

Hi, Yuuki

sorry for the late response because of Chinese New Year vacation.

yes, your understanding for i.mx6 is right.

I don't think i.mx28 has the same timg requirement as i.mx6.

while, 24M crystal is stable before ROM code running should be a MUST for i.mx28 since you don;t use 32.768k.

View solution in original post

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Contributor V

Hi, Weisong Liu-san

Thank you for your reply.

My problem was solved.

Best Regards,

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NXP Employee
NXP Employee

Hi, Yuuki

I cannot find the relationship parameter in all i.mx datasheet.

from my understanding:

24M clock must be satble when it's used in ROM code( ROM code is using 32K clock in early stage), so it's not be a mandatory requirement for 24M clock must be stable before RESET de-insetting.

but if 24M clock is stable before RESET de-insertting, it may very safe for the system.

the best solution I think is refer to i.mx6 reference design to add a 2.2M resistor to speed the start, anyway it's safe.

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Contributor V

Hi, Weisong Liu-san

Thank you for your reply.

The i.MX28 operates only with a 24MHz clock.
This time, 32K crystal is not used.

> (ROM code is using 32K clock in early stage)
=> This is a case of other devices, isn't it?

In the case of i.MX28, I understand that 24M clock must be stable before RESET de-insetting.


Is the ROM code started after checking that 24 MHz has been stabilized?

If there is no such structure,
How should I check that the 24MHz oscillation is stable before the ROM code starts?

Best Regards,

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NXP Employee
NXP Employee

Hi, Yuuki

i.mx28 has two kind of clock input configuration, one is your case which doesn't use 32.768k by fusing the "32k disbale" bit.

now I understand your case, in this case, the 24M clock MUST be stable before RESET signal de-inserting.

so please refer to refer to i.mx6 reference design to add a 2.2M resistor to XTALI.

till now, I don't see any customers meet the 24M timing issue on I.MX28.


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