About the relationship between HDMI gate clocks for i.MX8M Plus

[Chun1]

When I write the hdmi clock of imx8mp, I found that the relationship between gate clocks is not described in the document, but there is a corresponding mapping relationship in Linux code(drivers/clk/imx/clk-hdmimix.c).
eg, In Linux code , we known, the clock "hdmi_glb_apb" is the parent clock of the "hrv_mwr_apb", but the document doesn't describe it
Is there a corresponding description document here? The document I use is iMX_8M_Plus_RM_RevD.pdf. Thanks.

[joanxie]

could you send the source code about " the clock "hdmi_glb_apb" is the parent clock of the "hrv_mwr_apb"" to me? I couldn't find hdmi_glb_apb or hrw_mwr_apb in the clk-imx8mp.c, which code do you refer to? let me double check it

[Chun1]

I clone the code from link:https://source.codeaurora.org/external/imx/linux-imx

and  checkout to the branch: imx_5.4.70_2.3.0

the code is in `imx_hdmimix_clk_probe` function of the file `drivers/clk/imx/clk-hdmimix.c`.

In the file, you can see the "hdmi_glb_apb" and 'hrv_mwr_apb'

    clks[IMX8MP_CLK_HDMIMIX_FDCC_REF_CLK]      = imx_dev_clk_gate(dev, "hdmi_fdcc_ref",    "hdmi_fdcc_tst", base + 0x50, 2);
    clks[IMX8MP_CLK_HDMIMIX_HRV_MWR_APB_CLK]   = imx_dev_clk_gate(dev, "hrv_mwr_apb",       "hdmi_glb_apb", base + 0x50, 3);
    clks[IMX8MP_CLK_HDMIMIX_HRV_MWR_B_CLK]     = imx_dev_clk_gate(dev, "hrv_mwr_b",         "hdmi_glb_axi", base + 0x50, 4);
    clks[IMX8MP_CLK_HDMIMIX_HRV_MWR_CEA_CLK]   = imx_dev_clk_gate(dev, "hrv_mwr_cea",       "hdmi_glb_apb", base + 0x50, 5);
    clks[IMX8MP_CLK_HDMIMIX_VSFD_CEA_CLK]      = imx_dev_clk_gate(dev, "vsfd_cea",          "hdmi_glb_apb", base + 0x50, 6);
    clks[IMX8MP_CLK_HDMIMIX_TX_HPI_CLK]        = imx_dev_clk_gate(dev, "hdmi_tx_hpi",       "hdmi_glb_apb", base + 0x50, 13);
    clks[IMX8MP_CLK_HDMIMIX_TX_APB_CLK]        = imx_dev_clk_gate(dev, "hdmi_tx_apb",       "hdmi_glb_apb", base + 0x50, 14);
    clks[IMX8MP_CLK_HDMIMIX_TX_CEC_CLK]        = imx_dev_clk_gate(dev, "hdmi_cec",          "hdmi_glb_32k", base + 0x50, 15);
    clks[IMX8MP_CLK_HDMIMIX_TX_ESM_CLK]        = imx_dev_clk_gate(dev, "hdmi_esm",     "hdmi_glb_ref_266m", base + 0x50, 16);
    clks[IMX8MP_CLK_HDMIMIX_TX_GPA_CLK]        = imx_dev_clk_gate(dev, "hdmi_tx_gpa",       "hdmi_glb_apb", base + 0x50, 17);
    clks[IMX8MP_CLK_HDMIMIX_TX_PIXEL_CLK]      = imx_dev_clk_gate(dev, "hdmi_tx_pix",       "hdmi_glb_pix", base + 0x50, 18);
    clks[IMX8MP_CLK_HDMIMIX_TX_SFR_CLK]        = imx_dev_clk_gate(dev, "hdmi_tx_sfr",       "hdmi_glb_apb", base + 0x50, 19);
    clks[IMX8MP_CLK_HDMIMIX_TX_SKP_CLK]        = imx_dev_clk_gate(dev, "hdmi_tx_skp",       "hdmi_glb_apb", base + 0x50, 20);
    clks[IMX8MP_CLK_HDMIMIX_TX_PREP_CLK]       = imx_dev_clk_gate(dev, "hdmi_tx_prep",      "hdmi_glb_apb", base + 0x50, 21);
    clks[IMX8MP_CLK_HDMIMIX_TX_PHY_APB_CLK]    = imx_dev_clk_gate(dev, "hdmi_phy_apb",      "hdmi_glb_apb", base + 0x50, 22);
    clks[IMX8MP_CLK_HDMIMIX_TX_PHY_INT_CLK]    = imx_dev_clk_gate(dev, "hdmi_phy_int",      "hdmi_glb_apb", base + 0x50, 24);
    clks[IMX8MP_CLK_HDMIMIX_TX_SEC_MEM_CLK]    = imx_dev_clk_gate(dev, "hdmi_sec_mem", "hdmi_glb_ref_266m", base + 0x50, 25);
    clks[IMX8MP_CLK_HDMIMIX_TX_TRNG_SKP_CLK]   = imx_dev_clk_gate(dev, "hdmi_trng_skp",     "hdmi_glb_apb", base + 0x50, 27);
    clks[IMX8MP_CLK_HDMIMIX_TX_VID_LINK_PIX_CLK]= imx_dev_clk_gate(dev, "hdmi_vid_pix",     "hdmi_glb_pix", base + 0x50, 28);
    clks[IMX8MP_CLK_HDMIMIX_TX_TRNG_APB_CLK]   = imx_dev_clk_gate(dev, "hdmi_trng_apb",     "hdmi_glb_apb", base + 0x50, 30);

All clocks have no parent node description in the datasheet.

Thanks

[joanxie]

refer to the Table 5-1. Clock Root Table, you can find HDMI_APB_CLK_ROOT