Dear All,
There is description about SEQ_CLK_SPEED field of OTP PU CONFIG register in Start-up Sequence.
However, there is OTP PU CONFIG register from OTP PU CONFIG1 to OTP PU CONFIG3.
And, there is SEQ_CLK_SPEED[1:0] from SEQ_CLK_SPEED1[1:0] to SEQ_CLK_SPEED3[1:0].
Would you teach the reason that these 3 registers are here?
How should we use these registers?
http://cache.freescale.com/files/analog/doc/data_sheet/MMPF0100.pdf
- Table 12. Start-up Sequence (P.24)
- Table 13. Start-up Sequence Clock Speed (P.24)
- Table 137. Extended Page 1 (continued) (P.129)
Best Regards,
Yuuki
Solved! Go to Solution.
The SEQ_CLK_SPEEDx values are XORed to each other. The resulting SEQ_CLK_SPEED_XOR value (see on the same Table, the same Page) is then applied during the start-up sequence. The same is about the SWDVS_CLKx and PWRON_CFGx fields.
Have a great day,
Artur
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The SEQ_CLK_SPEEDx values are XORed to each other. The resulting SEQ_CLK_SPEED_XOR value (see on the same Table, the same Page) is then applied during the start-up sequence. The same is about the SWDVS_CLKx and PWRON_CFGx fields.
Have a great day,
Artur
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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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