About support EIM parallel NOR flash in u-boot

[RobbieJiang]

Hi,

I'm working on a mx6q board with LTIB-3.0.35_4.1.0.

My custom board is basically based on mx6q_sabrelite.

The system is booted from SPI serial NOR flash.

But we also have a parallel NOR flash attached on EIM CS0.

After U-boot boots from SPI NOR flash, it needs to access the parallel NOR flash.

The data width of the 64MB NOR is 8-bit and EIM works in asynchronous, non-multiplexed mode.

Here is the pad settings and EIM register setting in u-boot:

iomux_v3_cfg_t nor_pads[] = {
     MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16,
     MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17,
     MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18,
     MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19,
     MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20,
     MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21,
     MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22,
     MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23,

     MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0,
     MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1,
     MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2,
     MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3,
     MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4,
     MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5,
     MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6,
     MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7,
     MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8,
     MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9,
     MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10,
     MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11,
     MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12,
     MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13,
     MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14,
     MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15,
     MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16,
     MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17,
     MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18,

     MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19,
     MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20,
     MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21,
     MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22,
     MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23,
     MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24,
     MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25,

     MX6Q_PAD_EIM_OE__WEIM_WEIM_OE,
     MX6Q_PAD_EIM_RW__WEIM_WEIM_RW,
     MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0,

    MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK,

};

static void weim_norflash_cs_setup(void)

{
     /* EIM_CS0GCR1 */
     writel(0x00660081, WEIM_BASE_ADDR + 0x000);
     /* EIM_CS0GCR2 */
     writel(0x00000001, WEIM_BASE_ADDR + 0x004);
     /* EIM_CS0RCR1 */
     writel(0x1C022000, WEIM_BASE_ADDR + 0x008);
     /* EIM_CS0RCR2 */
     writel(0x0000C000, WEIM_BASE_ADDR + 0x00c);
     /* EIM_CS0WCR1 */
     writel(0x1404a38e, WEIM_BASE_ADDR + 0x010);
     /* EIM_CS0WCR2 */
     writel(0x00000000, WEIM_BASE_ADDR + 0x014);
     /* EIM_WCR: always enable BCLK output */
     writel(0x00000001, WEIM_BASE_ADDR + 0x090);
}

Other clock related registers are not touched,

and  IOMUXC_GPR1[2:0]  is set to '011'.

Also U-boot initializes CCGR1-CCGR6  to 0xFFFFFFFF,

which enables 'eim_slow_clk_enable'.

With the above initialize codes, I can not access the EIM nor flash.

And the EIM_BCLK pad does not output the expected clock signal.

By the way, with the same initialization code in my linux kernel,

I have managed to access the EIM NOR flash and got the clock signal on the EIM_BCLK pad.

What is missing in my u-boot?

Any suggestion is appreciated.

Thanks.

[zsjalive]

hey,you said you have successfully access to parell nor flash on CS0 in linux kernel, can you share you steps to have access to parrell nor flash in linux kernel,and how to code the driver code. better add you code file ,thanks

[igorpadykov]

Hi Robbie

parallel NOR is used in Sabre AI design i.MX6_SABRE_AI_DESIGNFILES

In Uboot ../mx6q_sabreauto folder one can look at EIM init function

weim_norflash_cs_setup()

also one can check if mmu is used in Uboot.

Best regards

igor

[RobbieJiang]

Hi igor,

Thanks for your information.

I have read the related code in mx6q_sabreauto folder.

Still I can't get EIM work by now.

Should the MMU be enabled to access EIM NOR flash?

But mx6q_sabreauto Uboot disables MMU.

And now I can get EIM_BCLK to output 132MHz clock,

but only after I try to read or write an address in the EIM range,

even if the EIM_WICR[BCM] = 1.

More suggestion?

Regards

Robbie

[igorpadykov]

Hi Robbie

BCLK can not work at 133MHz, it is too high.

One needs to decrease it using BCD

You can also try EIM example in SDK, then compare

EIM registers in SDK with Uboot (printf them)

i.MX 6Series Platform SDK : Bare-metal SDK

~igor

[RobbieJiang]

Finally, we managed to have the parallel EIM-NOR flash work with U-boot on mx6q_sabrelite board.

Here are the basic steps to do:

1. Define "CONFIG_CMD_WEIMNOR" in include/configs/mx6q_sabrelite.h

2. Undefine CONFIG_SYS_NO_FLASH  in this config file

3. Set the start address , the data widht of the NOR flash correctly in the same config file.

4. Add a function in mx6q_sabrelite.c to:

          Put the appropriate pads into correct mux mode;

          Set up the EIM control/configuration registers as required.

5.  Call this function in the board_init() function ( in board/freescale/mx6q_sabrelite/mx6q_sabrelite.c).

Most of the details can be found in the corresponding files for mx6q_sabreauto platform.

But one have to pay attention that this EIM initialization function has to be called before

the flash_init() function (in lib_arm/board.c), because the flash_init() function needs to

read some information from the flash chip, so before that , the EIM must be ready.

If you just call this EIM initialization function in board_init(),

then everything should be OK.