About special boot mode of eMMC4.3/4.4

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About special boot mode of eMMC4.3/4.4

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takayuki_ishii
Contributor IV

Hello community,

I have some basic question about eMMC4.3/4.4 special boot mode.

My understanding of the difference between special boot mode and normal boot mode

of boot ROM function is a memory location to read initial 4 KB of the program image must contain the IVT,
DCD, and the Boot Data structures.

  In special boot mode, initial 4KB image read from "BOOT area partition" in eMMC to internal OCRAM.

  In normal boot mode, initial 4KB image read from "USER area" in eMMC to internal OCRAM.

1) Is it correct?

    If so, how about main BOOT image?

    It will read from "User area" in both mode?

2) In "special boot mode", could it use plugin image?

3) How to select Boot partition1 or 2 to use it.

4) Table 8-15. SD/MMC frequencies in Reference Manual of i.MX6QP (IMX6DQPRM.pdf),

    Hi-speed of MMC(DDR mode) clock set to 50MHz.

    But boot flow from Figure 8-10 to Figure 8-16, it have no timing to set 50MHz.

    It have only 20 or 40 MHz setup.

    Which timing do eMMC clock set to 50MHz?

Best regards,

Ishii.

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takayuki_ishii
Contributor IV

Hello Yuri‌,

Sorry for my late reply.

I measured both MMC_CLK(ch2:Cyan) and MMC_CMD(ch1:Yello) with DDR fast boot setting.

(Shorted R712 : BT_CFG2_7 of SABRE-SD to set MMC4.4 8 or 4-bit DDR mode)

After power on, before start to copy 4KB data from BOOTPART1 to OCRAM,

To copy BOOTPART1, MMC_CLK work with 50MHz(Orange).

But befor copy it, MMC_CLK drive with 100MHz(Red). 

What is it doing?  

Is it a UHSI calibration function?

Best regards,
Ishii.

181002_mmccmd03.png

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Yuri
NXP TechSupport
NXP TechSupport

Hello,

  The special boot mode means boot mode of the eMMC, when “the master must

keep the CMD line LOW to read all of the boot data”; in such case the slave

recognizes that boot mode is being initiated and starts preparing boot data

internally. The partition from which the master will read the boot data can be selected

in advance using EXT_CSD byte [179], bits [5:3]. The data size that the

master can read during boot operation can be calculated as 128KB ×

BOOT_SIZE_MULT (EXT_CSD byte [226]).”

 

Please refer to eMMC4.3 (and higher) specs for more details.

 

 

Have a great day,

Yuri

 

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takayuki_ishii
Contributor IV

Hello Yuri,

Thank you for your quick response.

But what I want to know is how this partition is used in boot ROM.

In MMC/SD-Card boot, boot ROM copy 4KB boot image from sector 2 of MMC/SD card to internal RAM.

So user area(main storage) are parted to 4 area.

    user area      : MBR(sector 0,1) + u-boot(IVT+DCD) + FAT(zImage + .dtb file) + Ext4(Linux file system)

If eMMC4.3(or higher) use as boot device, it can use "Boot area partition" separated from the user area.

I think that it will parted as following.

    user area      : MBR(sector 0,1) + Ext4(Linux file system)

    boot partition : IVT+DCD + zImage + .dtb file

Is it correct?

If so, boot ROM in eMMC boot copy 4KB boot image from boot partition(in eMMC) to internal RAM(in i.MX6).

Is it correct?

Currently, my customer use plugin image, does it use with eMMC4.3(or higher) boot operation?

Best regards,

Ishii.

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Yuri
NXP TechSupport
NXP TechSupport

Hello, Ishii!

   According to Figure 8-17 (Expansion device structures layout) of i.MX 6Dual/6Quad RM, Rev. 4, 09/2017,
IVT, DCD, and the Boot Data structures are located separately (outside of device partitions).

pastedImage_1.png

Regards,

Yuri.

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takayuki_ishii
Contributor IV

Hello Yuri‌,

Do you mind answering about question 4)?

I think to set 50MHz emmc clock for DDR mode, it is just before to issue a switch command(CMD6)

to change bus width and DDR mode.(Figure 8-11. Expansion device (MMC) boot flow (2 of 6) in IMX6DQPRM rev1)

Is it correct?

Best regards,

Ishii.

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Yuri
NXP TechSupport
NXP TechSupport

  Boot ROM uses 40 MHz in the high-speed mode.

~Yuri.

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takayuki_ishii
Contributor IV

Hello Yuri,

Thank you for your quick response.

In Table 8-15 of IMX6DQPRM_rev1, Hi-speed mode MMC is 40MHz and Hi-speed mode MMC(DDR mode) is 50MHz.

Is this wrong?

Best regards,

Ishii.

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