About phy_rxclkactivehs register (MIPI-CSI2) in i.MX6DQ.

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About phy_rxclkactivehs register (MIPI-CSI2) in i.MX6DQ.

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keitanagashima
Senior Contributor I

Dear All,

Hello.

My customer is trying to connect the original camera to MIPI-CSI2 interface on MCIMX6Q-SDP.

But, the video signal (YUV422 1080p@30fps) can not be acquired right.

They checked the difference of MIPI-CSI2 register between original camera (Failed) and OV5640 (Success).

Below bit was different.

Refer to 40.6.6 General settings for all blocks (MIPI_CSI_PHY_STATE) in IMX6DQRM(Rev.2).

- Original camera (Failed) --> 0x230

- OV5640 (Success) --> 0x330

=====

Field 8 phy_rxclkactivehs

Indicates that the clock lane is actively receiving a DDR clock

Default Value: 0

=====

[Question]

Could you tell me the condition to become "phy_rxclkactivehs = 1"?

Best Regards,

Keita

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keitanagashima
Senior Contributor I

Dear Weidong,

Hello.

The issue was cleared by changing the setting steps between camera and i.MX6.

Thank you.

Best Regards,

Keita

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weidong_sun
NXP TechSupport
NXP TechSupport

Hello Keita,

     Could you tell me what "Original camera" means ? your meaning is it is a camera with 'RAW data' output , right ?

you know i.MX6 requires camera should have internal ISP and output should be RGB or YUV format, CSI can recieve RAW data with 'generic' mode, but do nothing after recieving data, so customer can't see anything on the screen.

     so phy_rxclkactivehs's value is not a root cause for the problem.

Regards,

Weidong

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keitanagashima
Senior Contributor I

Dear Weidong,

Hello.

The issue was cleared by changing the setting steps between camera and i.MX6.

Thank you.

Best Regards,

Keita

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richarddestiny
Contributor III

Hi,Keita

          how did you fixed the issue

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keitanagashima
Senior Contributor I

Dear Richard,

Sorry. I don't know the detail because the I got the answer from my customer.

But, I had gotten a little information from them.

==Customer's System==

MIPI device [MAX9288]  (Tx) --> i.MX6 MIPI-CSI2 (Rx)

==Steps==

1. Set the MAX9288 to "LPF" state.

2. Set the MIPI-CSI2 registers in i.MX6Q.

3. Change the MAX9288 to HS mode.

--> i.MX6 could receive the DDR clock.

Best Regards,

Keita

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keitanagashima
Senior Contributor I

Dear Weidong,

Hello.

Thank you for your reply.

> Could you tell me what "Original camera" means ? your meaning is it is a camera with 'RAW data' output , right ?

The video signal (YUV422 1080p@30fps).

[Original camera --> (YUV422) --> Serializer -----> Serializer to MIPI-CSI2 --> i.MX6DQ]

Best Regards,

Keita

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