About period between CS and next CS with DTACK mode in i.MX6DQ.

[keitanagashima]

Dear Sir or Madam,

Hello.

My customer is using EIM in DTACK mode with BCLK=100 MHz.

Refer to attached waveform.

The period of EIM_CSx_B=High (between CS active and CS active) =240 ns both of read/write.

They tuned up the CCM setting and the period shorted from 240 ns to 150 ns.

But, their target is less than 100 ns.

- Board: Custom board

- Software: Assembler code

- Other: No use the SDMA

Could you tell me the way of making short the interval of between CS active (Transfer data) and CS active (Transfer data)?

[Customer's setting]

EIM_CS1GCR1=01130481

EIM_CS1GCR2=00000300

EIM_CS1RCR1=01080000

EIM_CS1RCR2=00000008

EIM_CS1WCR1=81000000

EIM_CS1WCR2=00000000

Best Regards,

Keita

メッセージ編集者: Keita Nagashima

[igorpadykov · Accepted solution]

Hi Keita

interval between several active CSn can not be configured or shortened

and it is defined by internal buses latencies (including bus arbitration delays).

Period "240 ns to 150 ns" complies with data obtained from design.

Best regards

igor

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