About output display by external VSYNC in i.MX6SoloX.

[keitanagashima]

Dear All,

Hello. I have a question about output display by external VSYNC in i.MX 6SoloX.

Refer to attached file.

Is it possible to output image data from MX6SoloX by external VSYNC from FPGA ?

Best Regards,

Keita

[igorpadykov]

HI Keita

MX6SoloX can use VSYNC as input in MPU mode, this is described in

sect.37.4.7 VSYNC Interface i.MX6SX Reference Manual (rev.0  2/2015).

From sect.37.4.8.1 Code Example :  Vsync is always an output in the DOTCLK mode

http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6SXRM.pdf

Best regards

igor

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[keitanagashima]

Dear Igor,

Hello. Thank you for your reply.

I have additional questions.

[Q1]

>MX6SoloX can use VSYNC as input in MPU mode, this is described in

>sect.37.4.7 VSYNC Interface i.MX6SX Reference Manual (rev.0  2/2015).

You said "MPU mode".

Which is correct about your intention?

"37.4.6 MPU Interface" or "37.4.7 VSYNC Interface".

[Q2]

When i.MX6SX synchronize with VSYNC input,  is it possible to output pixel clock to FPGA?

I referred the "Figure 37-11. Timing in write mode of 6800 and 8080 protocols" in IMX6SX_Rev.0.

i.MX 6SoloX looks only support 6800 and 8080 protocols with VSYNC input.

Best Regards,

Keita

[igorpadykov]

HI Keita

1. this is MPU Interface, VSYNC interface is sort of MPU interface.

2. MPU Interface does not use output pixel clock

Best regards

igor

[keitanagashima]

Dear Igor,

Hello. Thank you for your reply.

I worried about transfer rate in the VSYNC interface.

Is it possible support the 720p (1280x720) resolution in the VSYNC interface of i.MX6SX?

(Refer to 1st attached timing spec "DispTiming(MX6SX&FPGA).xlsx​" again.)

Best Regards,

Keita

[igorpadykov]

HI Keita

MPU interface (VSYNC interface is kind of MPU interface)

is used for LCDs with internal memories, so called "smart" LCD.

Processor loads whole image to LCD, then LCD internally refresh it.

So if one uses "smart" LCD with 720p resolution such use case is possible.

Best regards

igor

[keitanagashima]

Dear Igor,

Hello. Thank you for your reply.

>So if one uses "smart" LCD with 720p resolution such use case is possible.

Thank you for your reply.

Yes. My customer will use the FPGA with internal memory.

The memory is small buffer with capacity of 10 lines (1280 x 10 lines).

Does i.MX6SX have the ability to transfer 720p@60fps? (xx MHz?)

Best Regards,

Keita

[igorpadykov]

HI Keita

I am afraid that such perfomance data is not available

since Sabre reference boards do not use MPU interface for LCDs.

Customer can test it himself and find experimentally what fps may be reached.

Best regards

igor

[keitanagashima]

Dear Igor,

Hello. Thank you for your reply.

Sorry, I have last question.

In the VSYNC Interface, after output 1 line data, is it possible to adjust by the line interval?

(Current line --> [wait] --> Next line)

Refer to attached timing requirement.

We want to set the interval of 3.7[us].

(I couldn't find the adjustable register in Reference Manual in VSYNC interface mode.)

Best Regards,

Keita

[igorpadykov · Accepted solution]

HI Keita

I am afraid this is not possible, since eLCDIF transmits all frame

data defined by the LCDIF_TRANSFER_COUNT, without [wait]

Best regards

igor

[keitanagashima]

Hi Igor,

Thank you very much.

I understood eLCD function with VSYNC interface.

Best Regards,

Keita