About more than one GPIO interrupt in i.MX6DQ.

[keitanagashima]

Dear All,

Hello.

I have a question about more than one GPIO interrupt in i.MX6DQ.

[Q1]

We will use the GPIO3_IO18 port (from external MCU) and GPIO3_IO31 port (from AUX audio) and set the GPIO3_GDIR/GPIO3_ICR2/GPIO3_IMR registers.

If above two interrupts input at the same time, How does the condition of GPIO3_ISR change? (I think It's very rare case.)

[Q2]

If above two interrupts input at the same time, Is two interrupt processings executed?

(We worry, that another interrupt is ignored.)

OS:L3.14.28_1.0.0

Best Regards,

Keita

[igorpadykov · Accepted solution]

Hi Keita

1. GPIO3_ISR will have two bits (18 and 31) set, corresponding for these events

2. it is customer responsibility to adequately process IRQ 103  - GPIO3 Combined interrupt indication for GPIO3 signals 16 - 31.

    He can service both interrupts in one ISR (interrupt service routine/exception call).

Best regards

igor

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[keitanagashima]

Dear Igor,

Thank you for your early reply.

>1. GPIO3_ISR will have two bits (18 and 31) set, corresponding for these events

OK. Thanks.

>2. it is customer responsibility to adequately process IRQ 103  - GPIO3 Combined interrupt indication for GPIO3 signals 16 - 31.

>    He can service both interrupts in one ISR (interrupt service routine/exception call).

I understood one interrupt (IRQ103) generate in GPIO3 group.

When I enter the next interruption from GPIO3_IO10 port,  how long is it necessary to wait?

Or, Is there any limitation? (Ex, Is it necessary to clear all GPIO3_ISR flag?)

Best Regards,

Keita

[igorpadykov]

Hi Keita

interupt latency or context switching one can find on link below

LMbench Benchmarks on i.MX

~igor

[keitanagashima]

Dear Igor,

OK.

Thank you for your support.

Best Regards,

Keita