About leak voltage by USB VBUS timing in i.MX6DQ.

[keitanagashima]

Dear All,

Hello.

I have a question about  leak voltage by USB VBUS timing in i.MX6DQ.

Refer to attached file.

And, please answer to me.

Best Regards,

Keita

[aven_tsao]

Hi Keita:

Q1. What is the cause of this leak voltage at the Case.1?

Ans. The leakage is from the the power-mux of internal USB LDO when switching the power source.

And the leakage will turns off when

Q2. Is there possibility of the destruction or malfunction of SoC by the leak voltage?

Ans. The leakage is located in power mux side , it will not affect to SoC.

Is it necessary to rise USB_OTG_VBUS and USB_H1_VBUS at the same time?

No need,

In case the USB Host port is enabled, the USB_H1_VBUS should be directly connected to a 5 V supply.

Best regards

Aven

[keitanagashima]

Hi Aven,

Please answer to my additional questions.

[Q1-1]

> Q1. What is the cause of this leak voltage at the Case.1?

> Ans. The leakage is from the the power-mux of internal USB LDO when switching the power source.

> And the leakage will turns off when

Last sentence looks blank (... turns off when ~ ??).

What did you answer last?

Best Regards,

Keita

[aven_tsao · Accepted solution]

HI Keita:

Sorry for my mistake.

The leakage is from the the power-mux of internal USB LDO when switching the power source.

And the leakage will turns off when the either input power source is valid.

Best regards

Aven

[keitanagashima]

Hi Aven, Karina

Thank you for your support.

>Sorry for my mistake.

No. problem.

Thank you very much!

Best Regards,

Keita

[karina_valencia]

AvenTsao​ please continue with the follow up.

[karina_valencia]

AvenTsao​ do you have an update?

[karina_valencia]

AvenTsao​ are you able to help here?