About layout of address and command signal in i.MX6 SABRE-AI.

[keitanagashima]

Dear Sir or madam,

Hello. I have a question about the layout of address and command signal in i.MX6 SABRE-AI.

Refer to "Table 3-3. DDR3 routing by byte group" in IMX6DQ6SDLHDG(Rev.1).

There were below descriptions.

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Min : Clock (min) – 200

Max : Clock (min)

Recommendations : Match the signals ± 25 mils.

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But, my customer measured the some address and command length on  i.MX6 SABRE-AI.

These length didn't match the signals "± 25 mils".

[Question]

Could you tell me the meaning of guide line?

"Match the signals ± 25 mils" means for all the signals of address and command?

or

"Match the signals ± 25 mils" means the matching four branched signals from output of single signal of i.MX6?

Best Regards,

Keita

[ahmetbolu]

Hello,

I was about to ask very similar question to community but i found this thread after couple of search about our issue. After Yuri's answer, now i can understand main guideline is hardware development guide not SABRE design. But i also have some additional questions about lenght matching:

1) What is the meaning of +-25?Is it allowed to use 975 mil 1000 mil and 1025 mil signals together in same address group? So it means 50 mil difference is allowed?

2) As we know the propogation delay of signals are different in microstrip (on top or bottom layers) with stripline(on internal layers) So our calculations shows that (for our pcb structure) the address lenght of 1000 mil signal on internal layer is equivalent to 1078 mil signal lenght of top/bottom layer. So what could be the best aproach to match these signals?:

*Match exact lenghts(without taking into acount the propogation delays)

*Match propogation delays (equivalent lenght)

3) Since some signals are not following the same structure of the address lines, do we have to taking via lenghts into considerations? Lets say an address line use one more via or one has Layer1 to Layer8 cross and one has Layer3 to Layer6. What would be the best approach?

[Yuri · Accepted solution]

  Address and Command lines (DRAM_A[15:0], DRAM_SDBA[2:0],

DRAM_RAS DRAM_CAS, DRAM_SDWE) should match (± 25 mils)

each other .

Have a great day,
Yuri

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[keitanagashima]

Hi Yuri,

Sorry. I have an additional question.

Do you know the other parameter which isn't matched with the design guide?

And, are there any issue when it isn't possible to be based on the design guide?

Best Regards,

Keita

[Yuri]

Keita, good day !

  It is known, that our boards (reference designs) sometimes violate recommended rules,

since often the boards are designed before or simultaneously with rules forming.  

What we can say - basically, the best approach - to use simulation technique for PCB design.

In the same time, general rules may be provided for customers to simplify their

PCB considerations, but note, for assurance such rules are very strong.

~Yuri.

[keitanagashima]

Hi Yuri,

Thank you for your great answer!

OK. I got it.

BR,

Keita