Hi gusarambula,
Thank you for your reply！
I use MSCALE_DDR_Tool to Calibration my board,when I download the DDR scprit, I can get the following output:
*************************************************************************
MX8 DDR Stress Test V2.10
Built on Mar 5 2019 14:26:42
*************************************************************************
--Set up the MMU and enable I and D cache--
- This is the Cortex-A53 core
- Check if I cache is enabled
- Enabling I cache since it was disabled
- Push base address of TTB to TTBR0_EL3
- Config TCR_EL3
- Config MAIR_EL3
- Enable MMU
- Data Cache has been enabled
- Check system memory register, only for debug
- VMCR Check:
- ttbr0_el3: 0x91d000
- tcr_el3: 0x2051c
- mair_el3: 0x774400
- sctlr_el3: 0xc01815
- id_aa64mmfr0_el1: 0x1122
- MMU and cache setup complete
*************************************************************************
ARM clock(CA53) rate: 800MHz
DDR Clock: 800MHz
============================================
DDR configuration
DDR type is DDR3
Data width: 16, bank num: 8
Row size: 15, col size: 10
Two chip selects are used
Number of DDR controllers used on the SoC: 1
Density per chip select: 512MB
Density per controller is: 1024MB
Total density detected on the board is: 1024MB
============================================
MX8M: Cortex-A53 is found
*************************************************************************
I think the tool is recognized my board, but when I click 'Calibration' , there was an error I got, as following:
============ Step 1: DDRPHY Training... ============
---DDR 1D-Training @800Mhz...
[Process] End of initialization
[Process] End of read enable training
[Process] End of fine write leveling
PMU: Error: dbyte 2 lane 0 failed read deskew
PMU: ***** Assertion Error - terminating *****
[Result] FAILED
What's that meaning? I changged several Regs value, It is the same error output. What should I do next?
The register configuration is in attachment.
thank you.
