About iMX6 BT1120 progressive output issure

cancel
Showing results for 
Search instead for 
Did you mean: 

About iMX6 BT1120 progressive output issure

487 Views
xionggao
Contributor II


Hello everyone,I have a custom iMX6Q board running 3.0.35_4.1.0.

I need to send 1080P video through the parallel display port to FPGA,here is our hardware design

pastedImage_1.png

I am using the latest BT.1120 patch by Qiang Li to set the video mode to 1080P50(Patch to Support BT656 and BT1120 Output For i.MX6 BSP ( L3.0.35_4.1.0_GA_bt656_output_patch_2016-06-24))

my uboot parameter is "video=mxcfb0:dev=bt656,BT1120-1080P50,if=BT1120,fbpix=RGB24"

I also change the BT656_IF_DI_MSB from 23 to 15.

After apply those changes, we can get right pixel clock 148.5MHz,but we can't get right data at the FPGA side.

then we try to find if 576P works.After change uboot paramter to "video=mxcfb0:dev=bt656,BT1120-576P,if=BT1120,fbpix=RGB24",we can get right pixel clock 27MHz,and we can get right data at FPGA side,but the V Freq is 25 Hz(the correct Freq is 50 Hz)

I also tried to change the 576P refresh rate from 25 to 50 in the driver/video/mxc/mxc_bt656if.c , but it seems no effect.

pastedImage_9.png

 

Here is my question:

1.How can i make the BT1120-576P V freq to 50 Hz ?

2.What's wrong with 1080P or am i doing any thing wrong?

3.how to understand the iMX6 IPU DC microcode template ? is there any example or resource availabe?  

4 Replies

98 Views
qiang_li-mpu_se
NXP Employee
NXP Employee

BT1120 has no VSYNC signal, they are embedded in data bus, so how did you check the V freq?

You also need double check the video mode by run command: "cat /sys/class/graphics/fb0/mode".

If your FPGA can get data at 27MHz and failed to get data at 148.5Mhz, you can reduce the pixel clock frequency to test, just make sure the protocol is correct. Maybe it is hardware interface issue, for high frequency pixel clock, the signal quality is also high.

For example:

 {
  /* 1080P50 Progressive output */
-  "BT1120-1080P50", 50, 1920, 1080, 6734,
+  "BT1120-1080P50", 50, 1920, 1080, 74074,

  41, 4,
  0, 0,
  720, 1,
  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  FB_VMODE_NONINTERLACED,
  FB_MODE_IS_DETAILED,},
  {

98 Views
xionggao
Contributor II

Thanks for your quick response,Li.

I test the protocol at lower frequency and it works.it  seems to be the hardware interface problem.

Besides,we get the V Freq by decode the data at the FPGA side.

But the framerate problem still existed.We can only get half the expected framerate.Why? 

0 Kudos

98 Views
qiang_li-mpu_se
NXP Employee
NXP Employee

For 1080P50 mode, the pixel clock is 148.5MHz, and there are total 1080+41+4 = 1125 lines for each frame.

For each line, there are 1920+720 = 2640 pixel clocks, so the frame rate = 148.5M / 1125 / 2640 = 50 fps.

The issue should be caused by your FPGA.

 {
  /* 1080P50 Progressive output */
  "BT1120-1080P50", 50, 1920, 1080, 6734,
  41, 4,
  0, 0,
  720, 1,
  FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  FB_VMODE_NONINTERLACED,
  FB_MODE_IS_DETAILED,},

98 Views
xionggao
Contributor II

thanks,I will double check that, Have a nice day.

0 Kudos