About i.MX6solo Ether MAC FIFO size.

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About i.MX6solo Ether MAC FIFO size.

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takayuki_ishii
Contributor III

Hello community,

Which size of TX/RX FIFO of Ether MAC of i.MX6solo?

In 23.2.1.1 Ethernet MAC features, it can show simple 64bit FIFO

• Simple 64-Bit FIFO user-application interface

The other hands, TFWR bit in Transmit FIFO Watermark Register (ENET_TFWR),

It can set from 64bytes to 4032bytes.

Does it have local FIFO memory for TX/RX FIFO each in MAC module?

or

"FIFO" indicate a ring buffer on external memory addressed by ENET_RDSR and ENET_TDSR?

Best regards,

Ishii.

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Yuri
NXP TechSupport
NXP TechSupport

takayuki_ishii 

Hello,

   Correct, the FIFO size is 4K bytes.

Regards,

Yuri,

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takayuki_ishii
Contributor III

Hello community,

I found a following sentence in 23.6.11 FIFO thresholds of Reference Manual IMX6SDLRM.

The thresholds are defined in 64-bit words.
The receive and transmit FIFOs both have a depth of 512 words.

Does ether MAC have 4KB(512wors x 64bit/word) local FIFO each TX and RX?

Best regards,

Ishii.

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Yuri
NXP TechSupport
NXP TechSupport

takayuki_ishii 

Hello,

   Correct, the FIFO size is 4K bytes.

Regards,

Yuri,

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takayuki_ishii
Contributor III

Hello Yuri,

Thank you for your quick response.

I understand that FIFO size is 4Kbyte.

Best regards,

Ishii.

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