Which size of TX/RX FIFO of Ether MAC of i.MX6solo?
In 188.8.131.52 Ethernet MAC features, it can show simple 64bit FIFO
• Simple 64-Bit FIFO user-application interface
The other hands, TFWR bit in Transmit FIFO Watermark Register (ENET_TFWR),
It can set from 64bytes to 4032bytes.
Does it have local FIFO memory for TX/RX FIFO each in MAC module?
"FIFO" indicate a ring buffer on external memory addressed by ENET_RDSR and ENET_TDSR?
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I found a following sentence in 23.6.11 FIFO thresholds of Reference Manual IMX6SDLRM.
The thresholds are defined in 64-bit words.
The receive and transmit FIFOs both have a depth of 512 words.
Does ether MAC have 4KB(512wors x 64bit/word) local FIFO each TX and RX?