About i.MX6q/d/sl cache controller and data aborts

[niranjandighe]

Hello All,

I am working on a automotive product based on i.MX6q and recently facing an issue where we see kernel error with message "imprecise external abort". I am trying to analyze it and need to know a few things (which are not very clear in the TRM) -

The i.MX6 uses the cache controller PL310 and the reference manual says -

"The cache controller gives support for sending L3 responses using the response lines of the AXI

protocol back to the processor that initiated the transaction. There are several methods to send

external error responses created by the L3.

The AXI protocol does not provide a method for passing back an error response that is not

combined with its original transaction.

The support provided enables the L1 master core to detect all L3 external aborts, as precise

aborts or as imprecise aborts through the interrupt lines."

I need to understand the highlighted line above. I am unable to find any interrupt line that notifies the processor about the aborts. Is it the case that this "interrupt line" refers to the data abort exception rather than a IRQ thereby calling data abort

exception handler instead of IRQ_handler and that this is a SoC/implementation specific thing?

Thanks in advance,

Niranjan Dighe

[igorpadykov]

Hi Niranjan

these errors may be caused by arm errata, described in IMX6DQCE

it may be recommended to use latest L3.14.28_1.0.0_iMX6QDLS_BUNDLE

which fixed some of them. Regarding PL310 interrupts on AXI bus transactions,

I would suggest post this question to arm support (www.arm.com).

Best regards

igor

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[niranjandighe]

Thanks Igor,

I understood that the PL310 reports the errors to the processor using IRQ line 124. However the freescale kernel (3.0.35_4.0.0, thats the one we use and it is not possible to upgrade right now.

The product is a live one and no kernel upgrade is possible immediately) does not seem to be using the IRQ line anywhere in the code. I did not see any request_irq or similar for this number.

1. Can I understand more clearly, how such errors are handled?

2. Can these in any way get translated to L1 cache errors thereby causing the Data Abort (imprecise and external)?

Best Regards,

Niranjan Dighe

[igorpadykov]

Hi Niranjan

from arm ARM Information Center

Imprecise data aborts

The state of the system presented to the abort exception handler for an imprecise

data abort can be the state for an instruction after the instruction that caused the abort.

As a result, it is not often possible to restart the processor from the point at which the

exception occurred.

from IMX6SDLCE Chip Errata for the i.MX 6Solo/6DualLite

Best regards

igor