About i.MX6Q EIM_WAIT setting in Asynchronous mode.

[keitanagashima]

Dear All,

In asynchronous mode, when the write / read access occurs during EIM_WAIT signal active, is it possible to delay the access until negating the EIM_WAIT signal?

(On customer's test, the write / read error happened.)

I have understood that the auto adjustment by EIM_WAIT signal support only in burst mode.

Best Regards,

Keita

[art]

The EIM_WAIT signal itself is not serviced in Asynchronous mode. However, on the EIM_WAIT pad, there is the I/O multiplexing option (ALT1) for EIM_DTACK that is the EIM Data Acknowledge signal. In Asynchronous access mode, EIM waits for the DTACK signal to be asserted and only then performs the data read/write operation. The DTACK signal polarity is configurable. So, in that meaning, it is possible to enlarge the EIM Asynchronous access time using the EIM_WAIT pad operating as DTACK (ALT1 IOMUX option). For more information, please refer to the Sections 22.5.14, 22.8.11 and 22.8.11 of the i.MX6Dual/Quad Reference Manual Rev.3 document.

Have a great day,
Artur

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[keitanagashima]

Hi Artur,

Sorry. I have an additional question.

My customer tried to test it by your comment (from EIM_WAIT to EIM_DTACK).

But, the access wasn't work correctly.

Do you find the cause of issue?

I send you the register setting.

=============

[IOMUX]
（Pad Mux Register）
0x020E0154        0x00000000        -->        0x00000001
（Pad Control Register）
0x020E0468        0x0001B0B0        -->        No change

[EIM]
EIM_CS2GCR1        0x00130001        -->        No change
EIM_CS2GCR2        0x00000000        -->        0x00000300
EIM_CS2RCR1        0x19001111        -->        No change
EIM_CS2RCR2        0x00000000        -->        No change
EIM_CS2WCR1        0x19000249        -->        No change
EIM_CS2WCR2        0x00000000        -->        No change

=============

Best Regards,

Keita

[Yuri]

Hello,

  EIM_WAIT functions as Data Acknowledge in asynchronous access.

According to section 22.5.14 (DTACK Mode) of the i.MX6 D/ Q RM :

“EIM begins the access and after a few cycles (according DAPS field) and

waits until DTACK (after synchronization) becomes asserted, then samples
the data in read access and completes the current data access”.

   So, strictly speaking, data latching is provided after DTACK asserted and

does not relate to negation this signal. Please refer to the Datasheet(s)

regarding parameters WE43 (Input Data Valid to EIM_CSx_B Invalid)
and WE44 (EIM_CSx_B Invalid to Input Data Invalid) about sample timings.

Have a great day,

Yuri

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