Hello,
You may use the EVK scheme as base. Possible modifications are as following :
1) DRAM_ADDR15 may be added ;
2) CS1 channel (DRAM_SDCKE1, DRAM_CS1_B, DRAM_ZQ1) may be implemented
for separate chip ;
3) Data bus DRAM_DATA[0-15] may be split between separate chips, assuming
control and address signals are the same for all chips.
You may send us Your design for review ( using Community or request Support|NXP )
Have a great day,
Yuri
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