About i.MX 7Dual Power mode transitions

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About i.MX 7Dual Power mode transitions

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goto11
Contributor III

Hello,community

About i.MX 7Dual Applications Processor Reference Manual, Table 6-8. Power mode transitions (Configuration with internal PMIC, Power mode (ON, first time))
If the voltage is applied only to VDD_SNVS_IN among the power supply terminals and POR_B is low, when the button is pressed, will 'state' be ON and PMIC_ON_REQ will be '1'?

Best Regards,

Goto

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weidong_sun
NXP TechSupport
NXP TechSupport

Hi,

 pastedImage_1.png

pastedImage_2.png

From diagram, we know logical relations:

FSM module will check time that button is pressed and kept, check if time <5s or >5s, determine power on or Power off.

Power On, PMIC_ON_REQ is HIGH or high Z, see above diagram.  Power Off , PMIC_ON_REQ =0.

Have a nice day!

BR,

Weidong

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weidong_sun
NXP TechSupport
NXP TechSupport

Hi,

  See schematic below first.

pastedImage_1.png

pastedImage_2.png

During power up, VSNVS is the first one, once it supplies VDD_SNVS_IN pin, SNVS_PMIC_ON_REQ pin will be pulled up to HIGH(VSNVS).

Have a nice day!

BR,

Weidong

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goto11
Contributor III

Hi,

About Table 6-8 and Figure 6-4 in i.MX 7 Dual Applications Processor Reference Manual
After the first VSNVS, until the ONOFF pin button in Figure 6-4 is pressed, is PMIC_ON_REQ still "0(Low)"?
Or is "1(high)" output for PMIC_ON_REQ regardless of the ONOFF pin button?
Is PMIC_ON_REQ output even if POR_B is "0(Low)" at this time?

Best Regards,

Goto

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575 Views
weidong_sun
NXP TechSupport
NXP TechSupport

Hi,

 pastedImage_1.png

pastedImage_2.png

From diagram, we know logical relations:

FSM module will check time that button is pressed and kept, check if time <5s or >5s, determine power on or Power off.

Power On, PMIC_ON_REQ is HIGH or high Z, see above diagram.  Power Off , PMIC_ON_REQ =0.

Have a nice day!

BR,

Weidong

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