Hello,Community
The following notes are listed in the superscript 1 of Table99 in the i.MX 7 Dual Family of Applications Processors Datasheet.
Is the following note not applicable to the PD / PU column?
Is the following note not applied during RESET?
note:The state immediately after RESET and before ROM firmware or software has executed.
Best Reguards,
Goto
Solved! Go to Solution.
Sorry, what I said before was for i.MX6 series processors. For i.MX7, these criteria are as follows.
- 1ms after the VDD_SOC_IN supply is valid
- 4ms after the NVCC_GPIOx supply is valid
Best Regards,
Artur
The Note you're referring to is applicable to the PD/PU column as well.
This is also applicable to the Power-On Reset state when both following conditions are met:
• 4ms after the external power supply VDDHIGH_IN is valid
• 1ms after the VDD_SOC_CAP supply is valid
except of the LCD1_DATA[19:00] pads that operate as the boot configuration signals.
Best Regards,
Artur
Hello,Community
Which names do VDDHIGH_IN and VDD_SOC_CAP correspond to in Figure 5-9. Power Diagram of i.MX 7 Dual Applications Processor Reference Manual?
What are the pin states in Table 99 in the i.MX 7 Dual Family of Applications Processors Datasheet until the following conditions are satisfied?
• 4ms after the external power supply VDDHIGH_IN is valid
• 1ms after the VDD_SOC_CAP supply is valid
Best Reguards,
Goto
Sorry, what I said before was for i.MX6 series processors. For i.MX7, these criteria are as follows.
- 1ms after the VDD_SOC_IN supply is valid
- 4ms after the NVCC_GPIOx supply is valid
Best Regards,
Artur