Hi jamesbone,
Thank you for your reply.
We think that the erratas are unrelated with the value of "32n+1" and the glitch...
I update the register information between SPI3 (No problem) and SPI5 (Problem).
When the error occur, FIFO overflow in status bit was seen.
Do you find another cause?
And does i.MX6 has difference setting between SPI3 and SPI5?
Best Regards,
Keita