About eCSPI read operation in i.MX 6.

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About eCSPI read operation in i.MX 6.

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keitanagashima
Senior Contributor I

Dear All,

We are using i.MX6Q as master and SPI device (Flash memory) is connected to.

We have encountered a problem of stopping the read operation while reading from the device by 256 byte unit via SPI.

(See attached file.)

- Port : eCSPI5

- SPI Frequency : 15MHz

- Frequency of Occurrence: Random (About 10%)

[Question]

Do you have any advice to resolve this issue?

Is there any limitations for eCSPI?

Is there any definition for the max size unit to be burst read via the SPI ?

Best Regards,

Keita

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keitanagashima
Senior Contributor I

Hi jamesbone,

Thank you for your reply.

We think that the erratas are unrelated with the value of "32n+1" and the glitch...

I update the register information between SPI3 (No problem) and SPI5 (Problem).

When the error occur, FIFO overflow in status bit was seen.

Do you find another cause?

And does i.MX6 has difference setting between SPI3 and SPI5?

Best Regards,

Keita

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694 Views
keitanagashima
Senior Contributor I

Dear All,

Do you have any update?

Best Regards,

Keita

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jamesbone
NXP TechSupport
NXP TechSupport

Hello Keita San,

This may be caused by i.MX6D ERR009165, ERR009606 i.MX6DQ Errata

http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf

 


Have a great day,
Jaime

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keitanagashima
Senior Contributor I

Dear All,

I update an additional information about this issue.

The error rate was improved by controlling the wait time (SAPLE_PERIOD bit in ECSPIx_PERODREG register)

Please refer to below test result.

["SAPLE_PERIOD" value : Error count / Test count]

00FF : 19/100

03FF : 18/100

07FF : 1/100

0FFF : 0/200

3FFF : 3/100

[Another information]

The issue happened by using eCSPI5.

When we use eCSPI3, the issue wasn't seen.

Best Regards,

Keita

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