Hi, NXP.
I want to implement hardware calibration for DDR3 with i.mx6ull. Is there any information available?I have checked the procedure in [i.MX 6 Series DDR Calibration.pdf], but I would like to obtain the source code.
~Background~
We are having problems with DDR3 calibration.
There have been many cases of mass-produced products suddenly stopping and freezing.
After investigating, it seems that there is a problem between DDR3 and i.mx6ull.
When I tried calibrating with a stress tool, the MPDGCTRL0 value seems to vary.
0x0130012c ~ 0x0158148
Is this range normal? Is it abnormal?
If you set this register to the optimal value for each individual device, it will work properly.
best regards.
