About addressing setting at QuadSPI Boot for i.MX6SoloX

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About addressing setting at QuadSPI Boot for i.MX6SoloX

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yuuki
Senior Contributor II

Dear all,

We refer to the following reference manual.

http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6SXRM.pdf

According to section 51.1.1 Features of QuadSPI in Reference Manual, the following contents are explained.

"•Supports 3-byte and 4-byte addressing."

And, according to section 51.5.3.11 Address scheme, the following contents are explained.

• Extended Address Mode
"By default, the QuadSPI is in 24-bit legacy address mode."

In section 8.6.2 QuadSPI Serial Flash BOOT Operation, it seems that The setting about the addressing mode does not be explained.

Does QuadSPI Serial Flash BOOT use only 3-byte addressing?
In addition, can Boot device be changed to 4-Byte addressing mode after Boot?

Best Regards,
Yuuki

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Pavel
NXP Employee
NXP Employee

Look at the Sections 51.7.3 and 8.6.2 of the IMX6SXRM.pdf file. These Section shows command sequence for QSPI booting. See these command sequences for changing 240bit addressing to 32-bit addressing of the QSPI Flash.


Have a great day,
Pavel

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Pavel
NXP Employee
NXP Employee

Look at the Sections 51.7.3 and 8.6.2 of the IMX6SXRM.pdf file. These Section shows command sequence for QSPI booting. See these command sequences for changing 240bit addressing to 32-bit addressing of the QSPI Flash.


Have a great day,
Pavel

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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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