About Stopping the CSI_PIXCLK of Gated Clock Mode Timing in i.MX6SL.

[keitanagashima]

Dear Sir or Madam,

Hello.I have a question about CSI_PIXCLK of Gated Clock Mode Timing in i.MX6SL.

Refer to "4.10.2.0.1 Gated Clock Mode Timing" in IMX6SLCEC_Rev.3.

There is below description.

"The pixel clock, CSI_PIXCLK (PIXCLK), is valid as long as HSYNC is asserted."

Is it possible to stop CSI_PIXCLK (PIXCLK) from external device, as long as HSYNC is de-asserted?

Best Regards,

Keita

[igorpadykov · Accepted solution]

Hi Keita

yes possible. Timing is similar to non-gated mode, RM shows it :

Best regards

igor

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