About Slave mode of Display Interface for i.MX6

[yuuki]

Dear all,

We want to synchronize the LVDS output with external CLK and VSYNC.
We have some questions.

1) "slave mode" is explained in section 37.1.2.1.2.2 Display Interface(P.2736) of IMX6DQRM.pdf(Rev2).
   What kind of usage does this mean?

   We think that the LVDS output can be synchronized by external CLK and VSYNC.
   Is our understanding right?

2) In Figure 37-39. DI's block diagram(P.2855), EXT_CLK and EXT_VSYNC are listed.

   However, these signals are not listed in Table 37-6. IPU1 External Signals(P.2747-).

   Which pin should these signals be input into each?

May I have advice?

Best Regards,

Yuuki

[igorpadykov]

Hi Yuuki

description in RM is generic, though IPU has external sync/clock signals,

depicted on Figure 37-39. DI's block diagram IMX6DQRM as EXT_VSYNC,EXT_CLK,

these signals are not routed externally for i.MX6.  EXT_CLK is connected internally as shows

Table 18-3 : ipp_di_ _ext_clk connected to ipu_di_clk_root.

Best regards

igor

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[yuuki]

Dear Igor-san,

Thank you for your support.

Would you answer the following question?

1) "slave mode" is explained in section 37.1.2.1.2.2 Display Interface(P.2736) of IMX6DQRM.pdf(Rev2).
   What kind of usage does this mean?

Best Regards,
Yuuki

[igorpadykov]

Hi Yuuki

in this mode display interface clock is

provided by an external source (slave mode).

Best regards

igor

[yuuki]

Dear Igor-san,

Thank you for your support.

Would you tell me the merit using slave mode?

Best Regards,

Yuuki

[igorpadykov]

Hi Yuuki

slave mode is using EXT_CLK, however this signal

not routed externally in i.MX6.

Best regards

igor