About STREAM_FENCING_CONTROL register for i.MX8X

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About STREAM_FENCING_CONTROL register for i.MX8X

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NXT_Kazuma_Sasaki
Senior Contributor I

Hello,

 

MIPI-CSI2 has STREAM_FENCING_CONTROL register. I have checked following VC enabling patch.

It seems like the STREAM_FENCING_CONTROL register is not using by linux BSP.

Could you please explain me feature of STREAM_FENCING_CONTROL register?

What does "Fence VC0" mean?

ISL79987 and adv7180 de-interlace driver for iMX8QXP boards 

From IMX8DQXPRM.pdf (Rev.0)

pastedImage_1.png

Best Regards,

Kazuma Sasaki.

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b45499
NXP TechSupport
NXP TechSupport

Hi Kazuma Sasaki

The stream_fencing is used to tell the MIPI CSI2 stop data transfer to pixel link.

For example, software can write "Fence VC0" to STREAM_FENCING_CONTROL register, then after MIPI CSI2 stops to transfer VC0 data to pixel link, the status "VC0 is fenced" can be read from STREAM_FENCING_STATUS register.

 

MIPI CSI2 reset can recover it.

Have a nice day

Best Regards,

Rita

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b45499
NXP TechSupport
NXP TechSupport

Hi Kazuma Sasaki

The stream_fencing is used to tell the MIPI CSI2 stop data transfer to pixel link.

For example, software can write "Fence VC0" to STREAM_FENCING_CONTROL register, then after MIPI CSI2 stops to transfer VC0 data to pixel link, the status "VC0 is fenced" can be read from STREAM_FENCING_STATUS register.

 

MIPI CSI2 reset can recover it.

Have a nice day

Best Regards,

Rita

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NXT_Kazuma_Sasaki
Senior Contributor I

Dear Rita Wang,

I appreciate your support. I got it.

Best Regards,

Kazuma Sasaki.