About SSI Receiver Timing with external clock.

[takayuki_ishii]

Hello community,

I have a question about fall edge hold timing of FS in slave mode SSI.

In Figure 93. of datasheet IMX6DQPAEC rev3, Hold time of falling edge of AUDx_TXFS are defined

as more than 10ns from AUDx_RXC high to AUDx_TXFS low(SS30 and SS34 of Table 85).

In this time, AUDx_TXFS and AUDx_RXD of Master device are transition by rise edge of AUDx_RXC.

And Slave device will be latched each signals by falling edge of AUDx_RXC.

If so, SS30 and SS34 of Table85, It is difficult to keep 10ns as hold time because it is transition timing.

Is it correct to define SS30 and SS34 as "AUDx_RXC high to AUDx_TXFS  low"?

I think that it should be define as a transition timing like SS28 or SS32 or

a hold time of AUDx_TXFS, it must define from falling edge of AUDx_RXC like a SS41.

I hope I can hear from you soon.

Best regards,

Ishii.

[igorpadykov · Accepted solution]

Hi Ishii

>in Figure 93. of datasheet IMX6DQPAEC rev3, Hold time of falling edge of AUDx_TXFS are defined
>as more than 10ns from AUDx_RXC high to AUDx_TXFS low(SS30 and SS34 of Table 85)...
>.. think that it should be define as a transition timing like SS28 or SS32

regarding your notes you are right, SS30 and SS34 timings should be depicted
as transition timing like SS28 or SS32.

Best regards
igor

[takayuki_ishii]

Hello Igor,

Thank you for your quick response.

Before update datasheet, is it ok to design SS30 and SS34 specification are not 10ns(min),

but same as SS28 and SS32(min=-10ns, max=15ns)?

Best regards,

Ishii.

[igorpadykov]

Hi Ishii

I think yes.

Best regards
igor

[takayuki_ishii]

Hello Igor,

Thank you for your response.

I will inform this answer to my customer.

Best regards,

Ishi.