About Power sequence in i.MX6SL.

[keitanagashima]

Dear All,

Hello. I have a question about Power sequence in i.MX6SL.

Refer to Table 7-3. Power sequence in Hardware Development Guide for i.MX 6SoloLite Applications Processor, Rev. 1.

There are two kind of power sequence at the Using all internal LDOs and Bypassed.

[Q1]

At the time of Power sequence, does the internal LDOs become invalid?

(Why are there two kind of sequence?)

[Q2]

Which correct description Data sheet or Hardware Design Guide?

(Description in Hardware Design Guide was hard requirement.)

Best Regards,

Keita

[Yuri]

Hello,

  The Datasheet provides most general approach / requirements for power
up sequence ; the Development Guide shows recommended example of power

sequencing. Different power up sequence for LDO enable and bypass is recommended

mainly to avoid excessive current during power-up phase.

Have a great day,
Yuri

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[keitanagashima]

Dear Yuri,

Hello. Thank you for your reply.

>  The Datasheet provides most general approach / requirements for power

> up sequence ; the Development Guide shows recommended example of power

> sequencing.

OK. I got it.

For example, VDD_HIGH_IN and NVCC33_IO were same timing from Development Guide.

But, these can separate the power sequence from data sheet.

> Different power up sequence for LDO enable and bypass is recommended

> mainly to avoid excessive current during power-up phase.

Sorry, I didn't understand it well.

How should one disable (bypass) the LDOs at the power-up phase.

My understanding was below.

Power-up phase is during POR_B asserted and the user can't select the bypass LDOs.

Best Regards,

Keita

[Yuri]

  Basically You are right : i.MX6 internal PMU enables LDO by default, so the

external input value must meet LDO enable mode requirement during power up.

After booting, SW can change to LDO bypass mode. In this sense it would be

better to remove the power up recommendations for LDO bypass mode.

Regards,

Yuri.

[keitanagashima]

Dear Yuri,

Hello. Thank you for your reply.

>In this sense it would be better to remove the power up recommendations for LDO bypass mode.

I think so, too.

We would like to remove this description.

Let me clarify below thing.

Refer to Note.1 in Table 7-3. Power sequence of Data sheet.

"Internally controlled by processor."

In case of the LDO enable (default), Power Up sequence looks controlled automatically by i.MX6.

If one power source supplies to i.MX6 with different sequence from "Table 7-3. Power sequence", does it become the sequence of "Table 7-3" by internal i.MX6?

Best Regards,

Keita

[Yuri]

  Internal sequencing basically does not depend on external voltage

supply sequence, assuming that corresponding inputs are provided :

  VDD_HIGH_IN should be applied to get VDD_HIGH_CAP.

Regards,

Yuri.

[keitanagashima]

Hi Yuri,

Thank you for your reply.

>Internal sequencing basically does not depend on external voltage

>supply sequence

Is it possible to ignore the Table 7-3. Power sequence in HDG because the sequence is controlled by i.MX6 internally?

I think that the user must meet the power sequence in data sheet .

Is my understanding OK?

Best Regards,

Keita

[Yuri · Accepted solution]

Yes, please follow Datasheet.

~Yuri.