Hello community.
I try to evaluate internal LDO of i.mx6QP.
In 52.7 PMU Memory Map/Register Definition of Reference manual IMX6DQPRM.
It have additional 3 registers for each PMU_REG_XXXX registers named _SET, _CLR and _TOG.
Does it funct that
It have only one PMU_REG_xxxx register and
to read/write each register address are effect to PMU_REG_xxxx register.
Is it correct?
Best regards,
Ishii.
Solved! Go to Solution.
Hi Ishii
yes your description and understanding is correct.
Best regards
igor
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Hi Ishii
yes your description and understanding is correct.
Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------
Hello Igor,
Thank you for your quick reply.
I will start to evaluate around internal LDO function.
Best regards,
Ishii.