About PF3000A4 SW2 output (3.3V) for i.MX6SL.

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About PF3000A4 SW2 output (3.3V) for i.MX6SL.

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keitanagashima
Senior Contributor I

Dear All,

MC32PF3000A4EP

Programming Options : 4 (i.MX 6 Series with DDR3)

In above ”A4” programming, SW2 output 3.3V (+-6%).

But, the VDD_HIGH, NVCC33_IO: 2.8Vmin - 3.3Vmax were defined by i.MX6SL.

Is it possible to use the MC32PF3000A4EP for i.MX6SL?

Best Regards,

Keita

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Yuri
NXP TechSupport
NXP TechSupport

Hello,

  App note AN5113 (Powering an i.MX 6SL Based System Using

the PF3000 PMIC) provides recommended configuration in Table 2 (PF3000 + i.MX 6SL

Power Tree), assuming LPDDR2 (preprogrammed A5 configuration).

http://cache.nxp.com/files/analog/doc/app_note/AN5113.pdf

  Nevertheless, considering the A4 case regarding 3.3V, note,

maximum GPIO and VDD_HIGH_IN supply voltage (Absolute Maximum Ratings) is 3.6V ; this

allows to decrease the SW2 output below 3.3V as soon as possible after boot for reliable

operation.

 

Have a great day,
Yuri

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Yuri
NXP TechSupport
NXP TechSupport

Hello,

  App note AN5113 (Powering an i.MX 6SL Based System Using

the PF3000 PMIC) provides recommended configuration in Table 2 (PF3000 + i.MX 6SL

Power Tree), assuming LPDDR2 (preprogrammed A5 configuration).

http://cache.nxp.com/files/analog/doc/app_note/AN5113.pdf

  Nevertheless, considering the A4 case regarding 3.3V, note,

maximum GPIO and VDD_HIGH_IN supply voltage (Absolute Maximum Ratings) is 3.6V ; this

allows to decrease the SW2 output below 3.3V as soon as possible after boot for reliable

operation.

 

Have a great day,
Yuri

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

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keitanagashima
Senior Contributor I

Hi Yuri,

Thank you for your reply.

>  App note AN5113 (Powering an i.MX 6SL Based System Using

>the PF3000 PMIC) provides recommended configuration in Table 2 (PF3000 + i.MX 6SL

>Power Tree), assuming LPDDR2 (preprogrammed A5 configuration).

OK. Thank you.

But, the target is DDR3(1.5V).

>  Nevertheless, considering the A4 case regarding 3.3V, note,

>maximum GPIO and VDD_HIGH_IN supply voltage (Absolute Maximum Ratings) is 3.6V ; this

>allows to decrease the SW2 output below 3.3V as soon as possible after boot for reliable

>operation.

OK. I got it.

Best Regards,

Keita

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mike_susen
NXP Employee
NXP Employee

Hi Keita,

Yes it is officially supported, see this https://www.nxp.com/webapp/search.partparamdetail.framework?PART_NUMBER=MC32PF3000A4EP

Michal

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keitanagashima
Senior Contributor I

Dear Michal,

Thank you for your prompt reply.

SW2 output 3.3V (+-6%) : Max 3.498V!

The voltage outs of operating range in i.MX6SL.

Is it possible to guarantee the voltage (3.498V) on VDD_HIGH, NVCC33_IO of i.MX6SL?

Best Regards,

Keita

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