About Non-Gated Clock Mode issue of the Parallel CSI module on the i.MX 6ULL series MPU.

[vikenzhou]

Hi, I am have a question about the Parallel CSI module, hope here can get answer, thank you!

When MPU is running  in Non-Gated Clock Mode, because the HSYNC signal will be ignored,
How know a line the number of pixels, it is possible using the clock edge to latched data;  if so,  in this Parallel_CSI_TX side, the pixel data of a line can many discontinuous clock cycles to send out ?
Please see below the figure,  thank you!

[vikenzhou]

Thans for your great support, the following questions please help guide again, thank you！
1, I have to see the pictures of you reply which is included a Data_EN signal, the signal in the Parallel_CSI_RX is necessary? The figure 19 on page758 of document  (IMX6ULLRM.pdf), Here is no use this Data_EN signal.
2, When sending a line of pixels, is the need for a continuous clock to send a line, or send a line of pixels can be discontinuous .

[joanxie · Accepted solution]

for non-gated mode, pls see the pic as below:

[vikenzhou]

Why in rev.1 Reference Manual there is no Data_EN .