About MIPI DSI in the i.MX 7Dual Applications Processor Reference Manual

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About MIPI DSI in the i.MX 7Dual Applications Processor Reference Manual

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goto11
Contributor III

Hello,

In the CLKLANE_STOP_START field of MIPI_DSI_CONFIG[30], there is an explanation of the operation when first HBP to second HFP for each VSYNC.
I seem to be able to turn off the clock lane on all VSYNC segments, what is the reason for such a control?

Regards,
Goto

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