About LVDS AC parameter in i.MX6DQ.

[keitanagashima]

Dear All,

Hello.

Refer to "Table 31. I/O AC Parameters of LVDS Pad" in IMX6DQAEC_Rev.3.

[Q1]

What does "Operating Frequency" parameter meaning?

(The parameter is Serializer clock, isn't it?)

[Q2]

Next, refer to Table 39-4. LDB Clock Sources in IMX6DQRM(Rev.2).

- interface serializer clock : Up to 595 MHz

Why is the max value "800MHz" in I/O AC Parameters of LVDS Pad?

Or, why is minimal value a blank?

[Q3]

Refer to "Table 39-2. LDB IP Parametric Table" in IMX6DQRM(Rev.2).

- IPU_DI0_CLK, IPU_DI1_CLK- Display interface clock: 20-170 MHz

- DI0_SERIAL_CLK, DI1_SERIAL_CLK - Serializer clock: 140-595 MHz

I consider that if one use the Dual channel mode, Serializer clock will be below formula.

• Dual Channel configuration

- Pixel clock: up to 170 MHz

- LVDS Clock frequency = Pixel clock x 7/2 = 170*7/2 = 595MHz

--> In case of Display interface clock: 20MHz, LVDS Clock frequency = 20MHz x 7/2 = 70MHz

So, I think that below spec is correct.

- DI0_SERIAL_CLK, DI1_SERIAL_CLK - Serializer clock: 70-595 MHz

Best Regards,

Keita

[art]

A1. Here, in the Table 31 of the i.MX6DQ Data Sheet, the "Operating Frequency" parameter means the possible switching frequency of the LVDS signals according to the LVDS I/O pad characteristics. For example, it means that each LVDS I/O signal theoretically can produce a square wave signal with the frequency of no more than 800MHz as per the Table data.

A2. As I told before, 800MHz is the maximum theoretical operating frequency of LVDS I/O pads.

Seems that the "minimum operating frequency" parameter is meaningless. If required, it can be established as per the specifications, listed in the Section 39.1.1 "Relevant Standards" of the Reference Manual document.

A3. It means that the serializer clock always must be x7 of the input pixel clock for each LVDS interface. Please refer to the Section 18.7.19 of the Reference Manual document for the information on the possible serializer clock sources.

Have a great day,
Artur

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[keitanagashima]

Hi Artur,

Thank you for your reply.

[A1][A2] --> Thank you very much.

[A3]

>A3. It means that the serializer clock always must be x7 of the input pixel clock for each LVDS interface.

Sorry. I understood it well...

Refer to Table 9-6. IP Parametric in IMX6DQRM(Rev.2).

----

DI0_CLK, DI1_CLK- Display interface clock: 20-170 MHz

DI0_SER_CLK, DI1_SER_CLK - Serializer clock: 140-595 MHz

----

If your answer is correct, I thought that Min value 20MHz x7 = 140MHz, Max value 170MHz x 7 = 1190MHz!

Should I consider separately the DIx_CLK and DIx_SER_CLK?

Best Regards,

Keita

[art · Accepted solution]

In case of the pixel clock frequency higher than 85MHz, a dual-interface LVDS scheme has to be used.

Have a great day,
Artur

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[keitanagashima]

Dear Autur,

Thank you for your great support.

My question is clearly!

Best Regards,

Keita