About I2S/ESAI sampling rate in i.MX6DQ.

[keitanagashima]

Dear All,

Hello. I have a question about I2S/ESAI sampling rate in i.MX6DQ.

Refer to "61.1.1 Features" in IMX6DQRM(Rev.3).

=========

Programmable I2S modes (Master, Slave or Normal). Maximum audio sampling rate

is 196kHz. (Note that maximum sampling rate depends on IPG frequency.)

=========

I calculated the bit clock from Data sheet spec.

Refer to "Table 86. SSI Transmitter Timing with Internal Clock" in IMX6DQAEC(Rev.4).

- SS1: AUDx_TXC/AUDx_RXC clock period = 81.4[ns]

- Bit clock = 1/81.4 [ns] = 12.285 [MHz]

- Max sampling frequency = 12.285 [MHz] / 64 = 191.95 [kHz]

  --> 191.95 [kHz] < 196 [kHz]

[Q1]

I think that max bit clock = 12.288 [MHz].

So, the AUDx_TXC/AUDx_RXC clock period will be "81.38 [ns]"

Is this a rounding error?

[Q2]

If Q1 is yes, Max sampling frequency will be 192 [kHz].

Does i.MX6DQ support to 196 [kHz]?

[Q3]

What is the meaning of "Note that maximum sampling rate depends on IPG frequency."

I didn't understand well.

Best Regards,

Keita

[Yuri]

Hello,

  Looks like You are right, the RM contains misprint about SSI sample frequency

of 196 kHz. The Datasheet states :

“SSI block capable of supporting audio sample frequencies up to 192 kHz stereo
inputs and outputs with I2S mode”.

192 kHz may be considered as rounding of 191.95 kHz in Your calculations.

To work with maximum frequency it is needed to provide proper module (IPG) frequency.

Say, the module cannot output frequency higher than its internal one.

Have a great day,
Yuri

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[keitanagashima]

Hi Yuri,

Thank you for your reply.

>  Looks like You are right, the RM contains misprint about SSI sample frequency

> of 196 kHz. The Datasheet states :“SSI block capable of supporting audio sample frequencies up to 192 kHz stereo

> inputs and outputs with I2S mode”.

> 192 kHz may be considered as rounding of 191.95 kHz in Your calculations.

OK. I got it.

I'd like to update you this description.

> To work with maximum frequency it is needed to provide proper module (IPG) frequency.

> Say, the module cannot output frequency higher than its internal one.

Sorry. I couldn't understand your meaning well.

Could you tell me the meaning of your answer again to understand easily?

Best Regards,

Keita

[Yuri]

  SSI Clocks, used for module operations are mentioined in section 61.3 (Clocks) of the i.MX6 DQ RM. 

Usually one of clocks is used for interfacing with internal system bus, and other - for module working.

Taking also into account output clocks, module proper functioning requires reasonable relations

between all clocks. To say roughly, hardly SSI can provide 12 MHz output, when ipg_clk_root = 1 KHz.

Regards,

Yuri

[keitanagashima]

Hi Yuri,

Thank you for your reply.

Ummm, I couldn't understand well.

Please tell me a below question.

[Question]

In the case of sample frequency (Fs) =192 kHz, what frequency should one set for "ipg_clk_root"?

We have recognized that the Fs clock is only related to "ccm_ssi_clk(ssi_clk_root)".

Best Regards,

Keita

[Yuri · Accepted solution]

Hi,

From section 61.8.4 (SSI Clocking) of the RM :
“Care should be taken to ensure that the bit clock frequency (either internally generated by

dividing the SSI's sys clock or sourced from external device through Tx/Rx clock ports)

is never greater than 1/5 of the ipg_clk (from CCM) frequency.”

Regards,

Yuri.