About Hight Resolution Audio correspond of i.MX6D.

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About Hight Resolution Audio correspond of i.MX6D.

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takashitakahash
Contributor III

Dear community.

Our customer has question below.

Customer would like to correspond to the Hi-Res of i.MX6DL.

In that case, we would want to SSI settings under the following specification.
I2S Slave mode
Fs = 96kHz
BitCLK = 6.144MHz (64Fs)
Bit Length = 24
In synchronization with the External CLK .

In accordance with 61.8.1.4 of IMX6DQRM.pdf
and considering trying to set the SSI_SCR, etc., but from a calculation of 61.8.4.2
I try to setting of the CLK will be DC = 1.66 ···.

What is do I best  to set these cases?

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igorpadykov
NXP Employee
NXP Employee

Hi Takahashi

 

I think this understanding is correct

Best regards
igor

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takashitakahash
Contributor III

Dear igor

Thank you for your answer.

Is my understanding correct?
As written below in P.5139 of IMX6DQ RM,
If FRAME_SYNC CLK and BIT CLK of I2S Slave mode it should be provided from an external codec.

below RM description.

The actual word length is determined by the external CODEC.

The external I2S Master still sends frame sync according to the I2S protocol

(early, word wide and active low), the SSI internally operates so that each frame sync

transition is the start of a new frame (the WL bits determine the number of bits to be

transmitted/received). After one data word has been transferred, the SSI waits for the next

frame sync transition to start operation in the next time slot. Transmit (STMSK) and

receive (SRMSK) mask bits should not be used in I2S Slave mode of operation. Masking

is supported only for network mode of operation.

Thank you,

Best Regards.

T.Takahashi

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igorpadykov
NXP Employee
NXP Employee

Hi Takahashi

 

I think this understanding is correct

Best regards
igor

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takashitakahash
Contributor III

Dear igor

Thank you for your answer.

Although this question is there is an assumption that in the I2S slave mode,
Do I can set the 64Fs in I2S slave mode?

Customers are demanding answers to up to 13th Oct..

Thank you,

Best Regards.

T.Takahashi

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igorpadykov
NXP Employee
NXP Employee

Hi Takahashi

I think yes, just for reference one can look at attached

sdk examples, check Chapter 32 Configuring the SSI Driver.

Best regards
igor

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igorpadykov
NXP Employee
NXP Employee

Hi Takashi

in my opinion one can formally use formula in sect.61.8.1.4,

assuming in I2S mode, DC=1 - two words per frame (left, right channel) :

f FRAME_SYN_CLK = (F INT_BIT_CLK) / [(DC + 1) x WL]  ==>
F INT_BIT_CLK= [(DC + 1) x WL] *f FRAME_SYN_CLK=
96KHz*2*24=4608KHz

Best regards
igor
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takashitakahash
Contributor III

Dear igor.

Thank you for your answer.

I have a question related to the answer.

1, About fFRAME_SYN_CLK, It is real Fs such that thing, If the system request Fs= 96kHz.
 Is it possible to set in fFRMAE_SYN_CLK = 96kHz?

2, Description of IMX6DQ RM of Page.5113, although there the actual word length is determined by the outside of the master,

Even if BITCLK comes in  64Fs at I2S slave mode,  generated by the internal
 FINT_BIT_CLK would be that clock to capture only the actual number of effective bits?

In other words, even as BITCLK = 64Fs from the outside, I think that that is capturing only valid data length set in WL bit in the inside?

3, When the setting of the DC was wrong, what kind of defect would be assumed?
 ※ When setting it as DC=3, please instruct about an assumed defect.

Thank you,

Best regards.

T.Takahashi.

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igorpadykov
NXP Employee
NXP Employee

Hi Takahashi

1. I believe yes

2.>Even if BITCLK comes in  64Fs at I2S slave mode,  generated by the internal
> FINT_BIT_CLK would be that clock to capture only the actual number of effective bits?

pastedImage_1.jpg

> I think that that is capturing only valid data length set in WL bit in the inside?

yes

3. behaviour could be unpredictable

Best regards
igor

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