About HSYNC timing of CSI input in i.MX6DQ.

[keitanagashima]

Dear Sir or Madam,

Hello.

My customer will use the camera input format with "YCbCr 16bits 1cycle [Y(8bits)+CbCr(8bits)] + HSYNC/VSYNC + DE”

I got the attached information from TIC (SR# 1-1147203261).

Refer to page.3 in attached file.

HSYNC becomes Active(High) only in the Active Line and, HSYNC seems to become Low during the blanking.

Is it necessary to make HSYNC Low during blanking?

Best Regards,

Keita

[Yuri · Accepted solution]

Keita,

  Yes, it is necessary to make HSYNC Low during blanking.
 

  For the Gated Clock Mode :
HSYNC goes to high and hold for the entire line. Pixel clock is valid as long as HSYNC is high.
Data is latched at the rising edge of the valid pixel clocks. HSYNC goes to low at the end of line.
Pixel clocks then become invalid and the CSI stops receiving data from the stream.

  For the Non-Gated Clock Mode – the HSYNC signal is not used.

Have a great day,
Yuri.

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[liyigang]

yuri muhin:

    how to make HSYNC Low during blanking,

if hsync is low during blanking , CSI0_HSYNC_POL should set to 0？

[keitanagashima]

Hi Yuri,

Thank you for your reply.

Sorry. I have additional questions.

Please check the attached file again.

And, is it support the input format in android jb4.2.2_1.1.0 for i.MX6Q?

Best Regards,

Keita

[Yuri]

Assuming the Gated Clock Mode :

1.
>  Is the "Valid pix_clk" of Figure1 right?                       

Yes.

2.
> Is the "entire line" of Figure1 right?                   

Yes.

3.
>  Is Figure2 right?                    

Yes.

Note, the Gated Clock Mode  is default one for parallel CSI cameras in BSPs.

Regards,

Yuri.

[keitanagashima]

Hi Yuri,

Hello.

Thank you for your reply.

Is it support the input format in android jb4.2.2_1.1.0 for i.MX6Q?

(Or, no dependent of the software?)

Best Regards,

Keita

[Yuri]

The Gated Clock Mode  is default one for parallel CSI cameras in BSPs.

Regards,

Yuri.

[keitanagashima]

Hi Yuri,

Thank you very much!

Best regards,

Keita