About EIM read access timing in i.MX6DQ.

[keitanagashima]

Hi All,

[Case]

The i.MX6 reads the data from external FPGA via EIM bus.

[Question]

When the FPGA outputs the WAIT & DATA signals to i.MX6, must the FPGA output the signals with the falling edge of EIM_BCLK from i.MX6?

(Because i.MX6 latches the WAIT & DATA signals with rising edge of EIM_BCLK.)

Best Regards,

Keita

[Yuri · Accepted solution]

Hello,

  Basically, any of previous clock edges may be used (rising, falling) ;

depending on internal FPGA delays.

Have a great day,
Yuri

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