About EIM burst access in i.MX6SL.

[keitanagashima]

Dear All,

Hello. I have questions about EIM burst access in i.MX6SL.

My customer will connect the FPGA via EIM on custom board and want to fix the FPGA's output timing.

[Q1] About Burst Read Memory Accesses

Refer to "20.8.7 Burst (Synchronous Mode) Read Memory Accesses Timing Diagram - BCD=0" in i.MX 6SoloLite Applications Processor Reference Manual, Rev. 2, 06/2015.

Is my below understanding right?

- Latch timing of control signals by FPGA is rising edge of BCLK.

- Output read data timing is falling edge of BCLK.

[Q2] About Burst Write Memory Accesses

Refer to "20.8.9 Burst (Synchronous Mode) Write Memory Access Timing - BCD=1" in i.MX 6SoloLite Applications Processor Reference Manual, Rev. 2, 06/2015.

Is my below understanding right?

- Latch timing of all signals (control & data) by FPGA is rising edge of BCLK.

[Q3]

I think that the register to select the BCLK polarity (rising or falling) doesn't exist in i.MX6SL.

Is it right?

Best Regards,

Keita

[Yuri · Accepted solution]

Hello,

1.

  According to the i.MX6SL Datasheet : “All EIM output control

signals may be asserted and deasserted by an internal clock synchronized
to the BCLK rising edge according to corresponding assertion/negation control
fields.”

   For data, from the Datasheet, table “EIM Bus Timing Parameters”, parameters

WE18 - Input data setup time to clock rise

WE19 - Input data hold time from clock rise

So, again, the rising edge is used.

2.

   For data, from the Datasheet, table “EIM Bus Timing Parameters”, parameters

WE16 - Clock rise to output data valid
WE17 - Clock rise to output data invalid

Rising edge is used.

3.

  Correct : “ […] the register to select the BCLK polarity (rising or falling) doesn't
exist in i.MX6SL.”

Have a great day,
Yuri

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