About DO_TRIM and DO_TRIM_PADN fields for SDCLK pad of i.MX6SoloX

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About DO_TRIM and DO_TRIM_PADN fields for SDCLK pad of i.MX6SoloX

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yuuki
Contributor V

Dear Freescale TIC,

We want to fine-tune High width and Low width of SDCLK.

We found that High width and the Low width of the clock were changed by changing DO_TRIM field and DO_TRIM_PADN field.

http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6SXRM.pdf

- 35.5.199 Pad Control Register IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P (P.1936-)

However, we were not able to find detailed explanation about DO_TRIM field and DO_TRIM_PADN field.

Would you tell me the usage of these field?

Can we use it to fine-tune High width and Low width of SDCLK?

Best Regards,
Yuuki

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Yuuki

DO_TRIM field allows to add delay from internal ipp_do signal

to SDCLK pad (ipp_do -> pad delay)

1.jpg

in general one can use this for changing width of SDCLK, however

usual way is to use MMDC Duty Cycle Control Register (MMDC_MPDCCR)

fields CK_FT0,1_DCC (p.2709 IMX6SXRM.pdf)

Best regards

igor

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Yuuki

DO_TRIM field allows to add delay from internal ipp_do signal

to SDCLK pad (ipp_do -> pad delay)

1.jpg

in general one can use this for changing width of SDCLK, however

usual way is to use MMDC Duty Cycle Control Register (MMDC_MPDCCR)

fields CK_FT0,1_DCC (p.2709 IMX6SXRM.pdf)

Best regards

igor

-----------------------------------------------------------------------------------------------------------------------

Note: If this post answers your question, please click the Correct Answer button. Thank you!

-----------------------------------------------------------------------------------------------------------------------

View solution in original post

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