About DDR3 DQ signal behavior by ODT changing in i.MX6DQ.

[keitanagashima]

Dear All,

Hello. I have a question about DDR3 DQ signal behavior by ODT changing in i.MX6DQ.

We measured the waveforms with changing ODT in i.MX6 or DDR3.

But, we didn't understand about result of measurement waveform.

[Q1]

Refer to "2. DDR ODT --> OFF @Custom board" in attached sheet.

In write operation, I think that the waveform quality should be changed by off the DDR3's ODT.

But, the waveform didn't be changed.

Why did it become such behavior?

[Q2]

Refer to "4. i.MX6 ODT --> OFF  && DDR ODT--> OFF" in attached sheet.

In write operation, I think that the waveform quality should not be changed by off the i.MX6's ODT.

But, the waveform quality became bad.

Why did it become such behavior?

This question is related to the following thread.

https://community.freescale.com/message/558926#558926

Best Regards,

Keita

[Yuri]

Hi,

  Let me look at DRAM initialization code - how DRAM ODT is modified.

Have a great day,
Yuri

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[keitanagashima]

Hi Mark and Yuri,

My customer measured the DQ signal with changing ODT again.

We could observed an intended waveform.

Thank you very much.

Refer to "4. DRAM ODT --> OFF (by Mode Register in DDR3)" in attached file.

The waveform didn't change by changing mode register in DDR3.

But, they are confirming this phenomenon to the DRAM maker.

Best Regards,

Keita

[keitanagashima]

Dear Yuri and Mark,

> You are turning on and off the ODT signal to the DRAM chip, correct?

> Are you able to access the MODT0 trace and do you see it high when ODT is set to turn on and do you see it low when ODT is set to turn off?

My customer is going to check the DDR setting & DRAM_SDODT0 signal again on next week.

So, I'll feedback asap on next week.

Best Regards,

Keita

[TheAdmiral · Accepted solution]

Hi Keita,

First let me define what I look at for signal quality:

1) Signal amplitude (ie, how high and how low the signal goes)

2) Signal slew rates (ie, how fast the signal rises and falls)

3) Are there any reflections seen in the falling or rising edges?

4) How much bounce at the peaks?

5) How rounded are the edges?

On your customer board, there does not appear to be any reflections, with or without ODT. This is a good design: Nothing abnormal about this condition.

At 528 MHz, there is little opportunity for overshoot/undershoot. This can also be effect by the Drive Strength level used.

Also at 528 MHz, I think the capacitance of the probe has more to do with rounding of the signals than does ODT.

So, in my opinion, the only visible evidence of ODT being set in or out is the amplitude levels and the slew rates.

Now, about your questions:

Between your pictures P1, P2, and P3, I do not see any change in amplitude of the signals. So I agree that it does not look like there are changes in ODT settings, even though they seem to be made.

One issue could be that ODT0 signal is not being used with CS0_B signal. But I checked your schematic and it looks like these are connected correctly.

The other issue could be that the MPODTCTRL registers are not set correctly. Could you please tell me your setting for this register: 0x021B0818?

Just to be thourough, what is the regsiter setting for IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 (0x020E059C)?

Are you able to access the MODT0 trace and do you see it high when ODT is set to turn on and do you see it low when ODT is set to turn off?

For question #2:

Picture P4 shows me a DQ signal amplitude of low = -235.6 mV and high = 1761.9 mV with ODT turned off.

Picture P5 shows me a DQ signal amplitude of low = 44 mV and high = 1463.9 mV with ODT turned on.

This is behaviour that I would expect. There is no reflection is either signal, but there doesn't necessarily have to be reflection with ODT turned off.

You are turning on and off the ODT signal to the DRAM chip, correct? There should be no effect if all you are changing are bits [18:4] of MPODTCTRL.

Cheers,

TheAdmiral​

[keitanagashima]

Hi Mark and Yuri,

Thank you for your reply.

I updated the information of customer's setting (MMDC and IOMUX).

Refer to attached file [i.MX6DQ_DDR3_ODT_ON-OFF_rev.4.xlsx].

> The other issue could be that the MPODTCTRL registers are not set correctly.

> Could you please tell me your setting for this register: 0x021B0818?

> Just to be thourough, what is the regsiter setting for IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 (0x020E059C)?

[Keita]

We had mis-understood about MPODTCTRL registers.

Refer to P4 in attached file. They had set MPODTCTRL = All 0.

(I think that DRAM_SDODT0 didn't active.)

> You are turning on and off the ODT signal to the DRAM chip, correct?

[Keita]

Refer to P2 in attached file.

I couldn't understand why did not change the waveform by setting the DDR3 mode register (RTT_WR=Dynamic ODT Disabled & RTT_NOM=ODT Disabled).

Please check the attached setting. 

> Are you able to access the MODT0 trace and do you see it high when ODT is set to turn on and do you see it low when ODT is set to turn off?

[Keita]

I ordered my customer it to measure with the DRAM_SDODT0 line.

Please wait.

Best Regards,

Keita