About DDR_PHY_OFFSET_RD_CON0 and DDR_PHY_OFFSET_WR_CON0 registers

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About DDR_PHY_OFFSET_RD_CON0 and DDR_PHY_OFFSET_WR_CON0 registers

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Contributor III

Hello,Community


The formula for calculating the offset time is Field value x tFS (tFS: fine step delay).
Which of the following 1 or 2 is correct for tFS?

1. There is a formula for calculating tFS in the CTRL_LOCK_VALUE column of the DDR_PHY_MDLL_CON1 register.
tFS = tCK / ctrl_lock_value [8: 0].

2. In "https://community.nxp.com/thread/445251", tFS is described as a fixed value as follows.
One delay value in this register is ~ 16.3 picoseconds.
This is equivalent to tFS (Fine Step delay).
This is a fixed value that does not vary with DDR clock frequency.
The register field values of 0x00-0x08 add no delay.For this field, 0x08 is effectively the zero starting point.
Every setting above 0x08 adds one tFS delay.
For example, a value of 0x12 adds 10 * tFS or 163 picoseconds of delay.

best regards

Goto

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NXP TechSupport
NXP TechSupport

Hello,

  It may be recommended to use the second approach.


Have a great day,
Yuri

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NXP TechSupport
NXP TechSupport

Hello,

  It may be recommended to use the second approach.


Have a great day,
Yuri

-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!

- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.

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