About CSI Gated Clock Mode in i.MX6DQ.

[keitanagashima]

Dear All,

I have a question about Gated Clock Mode in i.MX6DQ.

Refer to attached file.

Is it possible to input data right in Period 1 and Period 2?

Period 1 : 41508 pixclk (=1650pixel x 25line + 258pixel)

Period 2 : 8362 pixclk (=1650pixel x 5line + 112pixel）

[Condition]

- pixclk frequency : 74.25MHz

- Total Line count / frame (Blanking Line + Active Line) : 750

- Active Line count / frame (hsync count) : 720

- Total pixclk count / line (Included blanking) : 1650

- Active pixclk count / line : 1280

Best Regards,

Keita

[art]

In the Gated Clock mode, when the Hsync signal is inactive (low), no data capture is possible. Data is captured only when Hsync is active (high).

Have a great day,
Artur

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[keitanagashima]

Dear Autur,

Hello. Thank you for your reply.

>In the Gated Clock mode, when the Hsync signal is inactive (low), no data capture is possible.

>Data is captured only when Hsync is active (high).

Yes. We have already known above thing.

Refer to attached file again.

Is it possible to input data right with Period 1 and Period 2?

(Please consider the Period 1 and Period 2)

Best Regards,

Keita

[art · Accepted solution]

As per the diagram you've provided, the Period 1 overlaps the first active pclk clock, i.e. the first pclk clock when Vsync is active. So, at this moment, data is captured. Also, the Period 2 overlaps the last active pclk clock, i.e. the last pclk clock when Vsync is active. So, at this moment, data is captured as well.

Have a great day,
Artur

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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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[keitanagashima]

Hi Artur,

Thank you for your reply.

>i.e. the first pclk clock when Vsync is active

Is your meaning Hsync is active?

Do you find another problem?

Best Regards,

Keita

[art]

Oh, sorry.  Of course, I meant Hsync in both cases.

Best Regards,

Artur

[keitanagashima]

Hi Artur,

OK. Thank you very much!

Best Regards,

Keita