About CCM/clocking descriptions in IMX6SDLRM Rev. 2, 04/2015

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About CCM/clocking descriptions in IMX6SDLRM Rev. 2, 04/2015

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Contributor II

I'm confused about CCM/clocking.

For example,

in the Clock Tree figure Fig 18-3,

the divider: CSCMR2[LDB_DI0_IPU_DIV] is set to 1/7 as default.

But description in the "18.6.9 CCM Serial Clock Multiplexer Register 2 (CCM_CSCMR2)",

ldb_di0_ipu_div has reset value 0 and it means "divie by 3.5"

Which is correct ?

Also CS2CDR[LDB_DI0_CLK_SEL] can select MMDC_CH0 in the Clock Tree figure.

But at "18.6.12 CCM SSI2 Clock Divider Register (CCM_CS2CDR)",

ther

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Contributor II

mmm!

I'v noticed that reset value description on the CCM_CSCMR2 register (18.6.9) must be wrong.

A dwarf told me last night that "Deviated, about 4bits".

really?

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NXP TechSupport
NXP TechSupport

Hello,

What is value of CCM_CSCMR2  in Your case (in serial / USB boot mode of i.mx6 ) ?

Regards,

Yuri.

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Contributor II

Don't you think

reset value 0b011000=0x18=24 => 1/25 for can_clk_podf is obviously strange ?

It is described that default is 1/2=0x01=0b000001.

0b000001 is included in the default value but different place...

Or deviated is bit map assignments of each functions ?

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Contributor II

Thank you very much, Yuri.

4.

Dot marking for mux on the Clock tree means default selection.

...default selection set by boot-ROM, I see.

For me, as a firmware engineer, hardware reest value is not so usable if boot-ROM override it.

But as for the LSI engineers, boot-ROM action may not be his/her business, yes, I can realize it.

I wish the world that hardware reset valuies and boot-ROM config values both on the referece manual. ;-)

  (because .. "it is not possible to avoid it.")

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NXP TechSupport
NXP TechSupport

Hello,

As for boot ROM initialization, some information may be found in sections 8.4.2 (Boot Block Activation)

and 8.4.3 (Clocks at Boot Time) of the Reference Manual.

Regards,

Yuri.

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NXP TechSupport
NXP TechSupport

Hello,

  Please look at my comments :


1.

CSCMR2[LDB_DI0_IPU_DIV] is set to 1/7 as default - this is correct.

2.

CS2CDR[LDB_DI0_CLK_SEL] can select MMDC_CH1 - this is correct.

Have a great day,
Yuri

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Contributor II

Thank you for your response, Yuri.

1.

CSCMR2[LDB_DI0_IPU_DIV] is set to 1/7 as default - this is correct.

It means that the boot-ROM sets LDB_DI0_IPU_DIV bit to '1' ?

Are there 2 kind of reset values that:

(1) hardware reser value

(2) initial values set by boot-ROM     ??

2.

CS2CDR[LDB_DI0_CLK_SEL] can select MMDC_CH1 - this is correct.

It mesns the Clock Tree figure is not so relayable ?

I shall believe register description details than that figure ?

And one more...

At "18.6.15 CCM Serial Clock Divider Register 2 (CCM_CSCDR2)",

epdc_pix_clk_sel has reset value '101' but it is 'reserved' in the following description.

What meaning of the MUX dot marking in the Clock Tree for CSCDR2[EPDC_PIX_PODF] ?

(I'm talking about 6Solo, its internal frequency limits/recommendations are a little bit different from 6Dual...)

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NXP TechSupport
NXP TechSupport

Hello,

1.

> CSCMR2[LDB_DI0_IPU_DIV] is set to 1/7 as default
I checked it on my board with JTAG, after boot ROM (it is not possible to avoid it).

2.
> It means the Clock Tree figure is not so reliable ?

Alas, misprints may take place :-(

3.

epdc_pix_clk_sel = 0


4.
Dot marking for mux on the Clock tree means default selection.

Regards,

Yuri.

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